Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9830ASTZ

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AD9830

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700 Fax:

FEATURES

+5 V Power Supply

50 MHz Speed

On-Chip SINE Look-Up Table

On-Chip 10-Bit DAC

Parallel Loading

Power-Down Option

72 dB SFDR

250 mW Power Consumption

48-Pin QFP

APPLICATIONS

DDS Tuning

Digital Demodulation

GENERAL DESCRIPTION

This DDS device is a numerically controlled oscillator em-

ploying a phase accumulator, a sine look-up table and a

10-bit D/A converter integrated on a single CMOS chip.

Modulation capabilities are provided for phase modulation

and frequency modulation.

Clock rates up to 50 MHz are supported. Frequency accu-

racy can be controlled to one part in 4 billion. Modulation

is effected by loading registers through the parallel micro-

processor interface.

A power-down pin allows external control of a power-down

mode. The part is available in a 48-pin QFP package.

FUNCTIONAL BLOCK DIAGRAM

RESET

SLEEP

IOUT

COMP

REFINFS ADJUSTREFOUTAGNDAVDD

DGNDDVDD

MCLK

FSELECT

D15

A0 A1 A2 PSEL0 PSEL1

AD9830

ON-BOARD

REFERENCE

FULL SCALE

CONTROL

10-BIT DAC

SIN

ROM

PHASE

ACCUMULATOR

(32-BIT)

MUX

FREQ0 REG

FREQ1 REG

PHASE0 REG

PHASE1 REG

PHASE2 REG

PHASE3 REG

PARALLEL REGISTER TRANSFER CONTROL

MPU INTERFACE

REV. B

2011

781-461-3113

DIRECT DIGITAL SYNTHESIZER,

WAVEFORM GENERATOR

http://www.analog.com/DDS.

Similar DDS products can be found at

Summary of content (16 pages)

PAGE 1
a DIRECT DIGITAL SYNTHESIZER, WAVEFORM GENERATOR AD9830 FEATURES +5 V Power Supply 50 MHz Speed On-Chip SINE Look-Up Table On-Chip 10-Bit DAC Parallel Loading Power-Down Option 72 dB SFDR 250 mW Power Consumption 48-Pin LQFP GENERAL DESCRIPTION APPLICATIONS DDS Tuning Digital Demodulation A power-down pin allows external control of a power-down mode. The part is available in a 48-pin LQFP package.
PAGE 2
AD9830–SPECIFICATIONS1 R(V DD SET Parameter SIGNAL DAC SPECIFICATIONS Resolution Update Rate (fMAX) IOUT Full Scale Output Compliance DC Accuracy Integral Nonlinearity Differential Nonlinearity = +5 V 6 5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT; = 1 kV; RLOAD = 51 V for IOUT and IOUT unless otherwise noted) AD9830A Units Test Conditions/Comments 10 50 20 1 Bits MSPS max mA max V max ±1 ± 0.
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AD9830 TIMING CHARACTERISTICS (V DD = +5 V 6 5%; AGND = DGND = 0 V, unless otherwise noted) Parameter Limit at TMIN to TMAX (A Version) Units Test Conditions/Comments t1 t2 t3 t4 1 t4A1 t5 t6 t7 t8 t9 1 t9A1 t10 20 8 8 8 8 8 t1 5 3 8 8 t1 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min MCLK Period MCLK High Duration MCLK Low Duration WR Rising Edge Before MCLK Rising Edge WR Rising Edge After MCLK Rising Edge WR Pulse Width Duration Between Consecutive WR Pulses
PAGE 4
AD9830 Maximum Junction Temperature . . . . . . . . . . . . . . . . LQFP θJA Thermal Impedance . . . . . . . . . . . . . . . . . Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 5
AD9830 PIN DESCRIPTION Mnemonic Function POWER SUPPLY AVDD Positive power supply for the analog section. A 0.1 µF capacitor should be connected between AVDD and AGND. AVDD has a value of +5 V ± 5%. AGND Analog Ground. DVDD Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between DVDD and DGND. DVDD has a value of +5 V ± 5%. DGND Digital Ground. ANALOG SIGNAL AND REFERENCE IOUT, IOUT Current Output. This is a high impedance current source.
PAGE 6
AD9830 TERMINOLOGY Output Compliance Integral Nonlinearity The output compliance refers to the maximum voltage which can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compliance are generated, the AD9830 may not meet the specifications listed in the data sheet. For the AD9830, the maximum voltage which can be generated by the DAC is 1V.
PAGE 7
Typical Performance Characteristics–AD9830 –35 60 50MHz –40 SFDR (0–MCLK/2) – dB TOTAL CURRENT – mA 55 AVDD = DVDD = +5V TA = +25°C fOUT = 200kHz 50 45 40 –45 30MHz –50 10MHz –55 –60 35 AVDD = DVDD = +5V 30 10 –65 20 30 40 MCLK FREQUENCY – MHz 0 50 0.05 0.1 0.15 0.2 fOUT/fMCLK 0.25 0.3 0.35 Figure 8. WB SFDR vs. fOUT/fMCLK for Various MCLK Frequencies Figure 5. Typical Current Consumption vs.
PAGE 8
0 0 –10 –10 –20 –20 –30 –30 10dB/DIV 10dB/DIV AD9830 –40 –50 –60 –70 –70 –80 –80 VBW 3kHz –90 START 0Hz RBW 1kHz STOP 25MHz ST 50 SEC Figure 11. fMCLK = 50 MHz, fOUT = 2.1 MHz, Frequency Word = ACO8312 0 0 –10 –10 –20 –20 –30 –30 –40 –50 –50 –60 –70 –70 –80 –80 VBW 3kHz –90 START 0Hz RBW 1kHz STOP 25MHz ST 50 SEC Figure 12. fMCLK = 50 MHz, fOUT = 3.
PAGE 9
AD9830 0 –10 –20 10dB/DIV –30 –40 –50 –60 –70 –80 –90 START 0Hz RBW 1kHz STOP 25MHz ST 50 SEC VBW 3kHz Figure 17. fMCLK = 50 MHz, fOUT = 16.5 MHz, Frequency Word = 547AE148 Register Size Description A2 A1 A0 Destination Register FREQ0 REG 32 Bits FREQ1 REG 32 Bits PHASE0 REG 12 Bits Frequency Register 0. This defines the output frequency, when FSELECT = 0, as a fraction of the MCLK frequency. Frequency Register 1.
PAGE 10
AD9830 CIRCUIT DESCRIPTION Numerical Controlled Oscillator + Phase Modulator The AD9830 provides an exciting new level of integration for the RF/Communications system designer. The AD9830 combines the Numerical Controlled Oscillator (NCO), SINE Look-Up table, Frequency and Phase Modulators, and a Digital-to-Analog Converter on a single integrated circuit. The internal circuitry of the AD9830 consists of three main sections.
PAGE 11
AD9830 FSELECT, PSEL0 and PSEL1 are sampled on the MCLK rising edge. Again, these inputs should be valid when an MCLK rising edge occurs as there will be an uncertainty of one MCLK cycle introduced otherwise. When these inputs change value, there will be a pipeline delay before control is transferred to the selected register—there will be a pipeline delay before the analog output is controlled by the selected register. Similarly, there is a delay when a new word is written to a register.
PAGE 12
AD9830 APPLICATIONS The AD9830 contains functions which make it suitable for modulation applications. The part can be used to perform simple modulation such as FSK. More complex modulation schemes such as GMSK and QPSK can also be implemented using the AD9830. In a FSK application, the two frequency registers of the AD9830 are loaded with different values, one frequency will represent the space frequency while the other will represent the mark frequency.
PAGE 13
AD9830 Grounding and Layout The printed circuit board that houses the AD9830 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place.
PAGE 14
AD9830 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH VIEW A 24 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 051706-A 0.15 0.05 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35 Figure 1.
PAGE 15
AD9830 NOTES Rev.