Datasheet

AD9830
–3–
TIMING CHARACTERISTICS
Limit at
T
MIN
to T
MAX
Parameter (A Version) Units Test Conditions/Comments
t
1
20 ns min MCLK Period
t
2
8 ns min MCLK High Duration
t
3
8 ns min MCLK Low Duration
t
4
1
8 ns min WR Rising Edge Before MCLK Rising Edge
t
4A
1
8 ns min WR Rising Edge After MCLK Rising Edge
t
5
8 ns min WR Pulse Width
t
6
t
1
ns min Duration Between Consecutive WR Pulses
t
7
5 ns min Data/Address Setup Time
t
8
3 ns min Data/Address Hold Time
t
9
1
8 ns min FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge
t
9A
1
8 ns min FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge
t
10
t
1
ns min RESET Pulse Duration
NOTES
1
See Pin Description section.
Guaranteed by design, but not production tested.
t
1
t
2
t
3
t
4A
t
4
t
5
t
6
MCLK
WR
Figure 2. WR –MCLK Relationship
A0, A1, A2
DATA
WR
t
6
t
8
t
7
t
5
VALID DATA VALID DATA
Figure 3. Writing to a Phase/Frequency Register
t
9
VALID DATA VALID DATA VALID DATA
t
9A
t
10
MCLK
FSELECT
PSEL0, PSEL1
RESET
Figure 4. Control Timing
(V
DD
= +5 V 6 5%; AGND = DGND = 0 V, unless otherwise noted)
REV. B