25 MHz Direct Digital Synthesizer, Waveform Generator AD9832 Data Sheet FEATURES GENERAL DESCRIPTION 25 MHz speed On-chip SIN lookup table On-chip, 10-bit DAC Serial loading Power-down option Temperature range: −40°C to +85°C 200 mW power consumption 16-Lead TSSOP The AD9832 is a numerically controlled oscillator employing a phase accumulator, a sine look-up table, and a 10-bit digitalto-analog converter (DAC) integrated on a single CMOS chip.
AD9832 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Latency ......................................................................................... 16 Applications ....................................................................................... 1 Flowcharts ................................................................................... 16 General Description ..........................................
Data Sheet AD9832 SPECIFICATIONS VDD = +5 V ± 5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT; RSET = 3.9 kΩ; RLOAD = 300 Ω for IOUT, unless otherwise noted. Also, see Figure 2. Table 1.
AD9832 Data Sheet RSET 3.9kΩ 10nF ON-BOARD REFERENCE 12 SIN ROM REFIN FS ADJUST FULL-SCALE CONTROL 10-BIT DAC COMP AVDD 10nF IOUT 300Ω 50pF AD9832 Figure 2. Test Circuit by Which Specifications Were Tested Rev.
Data Sheet AD9832 TIMING CHARACTERISTICS VDD = +5 V ± 5%; AGND = DGND = 0 V, unless otherwise noted. Table 2.
AD9832 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND DVDD to DGND AVDD to DVDD AGND to DGND Digital I/O Voltage to DGND Analog I/O Voltage to AGND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD Rating Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to DVDD + 0.
Data Sheet AD9832 FS ADJUST 1 16 COMP REFIN 2 15 AVDD REFOUT 3 14 IOUT DVDD 4 AD9832 13 AGND DGND 5 TOP VIEW (Not to Scale) 12 PSEL0 MCLK 6 11 PSEL1 SCLK 7 10 FSELECT SDATA 8 9 FSYNC 09090-006 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No.
AD9832 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 25 –40 TA = 25°C AVDD = DVDD = 3.3V –45 –50 SFDR (±2MHz) (dB) TOTAL CURRENT (mA) 20 15 5V 10 3.3V 25MHz –55 10MHz –60 –65 –70 5 5 15 10 20 25 MCLK FREQUENCY (MHz) –80 09090-007 0 0 0.1 0.2 0.4 0.3 fOUT/fMCLK 09090-010 –75 Figure 10. Wideband SFDR vs. fOUT/fMCLK for Various MCLK Frequencies Figure 7. Typical Current Consumption vs. MCLK Frequency –50 60 AVDD = DVDD = 3.3V fOUT = fMCLK/3 fOUT/fMCLK = 1/3 AVDD = DVDD = 3.
Data Sheet AD9832 0 10.0 AVDD = DVDD = 2.97V –10 –20 –30 10dB/DIV WAKE-UP TIME (ms) 7.5 5.0 –40 –50 –60 –70 2.5 –80 –30 –20 –10 0 TEMPERATURE (°C) –100 09090-013 0 –40 0 –10 –20 –20 –30 –30 –40 –40 10dB/DIV –50 –60 –50 –60 –70 –70 –80 –80 VBW 1kHz STOP 12.5MHz ST 277 SEC 09090-014 START 0Hz RBW 300Hz –100 Figure 14. fMCLK = 25 MHz, fOUT = 1.1 MHz, Frequency Word = 0xB439581 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC 09090-017 –90 –90 Figure 17.
Data Sheet 0 0 –10 –10 –20 –20 –30 –30 –40 –40 10dB/DIV –50 –60 –60 –70 –70 –80 –80 –90 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC –100 Figure 19. fMCLK = 25 MHz, fOUT = 6.1 MHz, Frequency Word = 0x3E76C8B4 –10 –10 –20 –20 –30 –30 –40 –40 10dB/DIV 0 –50 –60 –60 –80 –80 –90 –90 STOP 12.5MHz ST 277 SEC 09090-020 –70 VBW 1kHz –100 Figure 20. fMCLK = 25 MHz, fOUT = 7.1 MHz, Frequency Word = 0x48B43958 STOP 12.
Data Sheet AD9832 TERMINOLOGY Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 . . . 00 to 000 . . . 01) and full scale, a point 0.5 LSB above the last code transition (111 . . . 10 to 111 . . . 11). The error is expressed in LSBs.
AD9832 Data Sheet THEORY OF OPERATION Sine waves are typically thought of in terms of their magnitude form a(t) = sin (ωt). However, these are nonlinear and not easy to generate except through piecewise construction. On the other hand, the angular information is linear in nature. That is, the phase angle rotates through a fixed angle for each unit of time. The angular rate depends on the frequency of the signal by the traditional rate of ω = 2 πf.
Data Sheet AD9832 CIRCUIT DESCRIPTION The input to the phase accumulator (that is, the phase step) can be selected from either the FREQ0 register or the FREQ1 register and can be controlled by the FSELECT pin or the FSELECT bit. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. The AD9832 provides an exciting new level of integration for the RF/communications system designer.
AD9832 Data Sheet FUNCTIONAL DESCRIPTION SERIAL INTERFACE Table 6. Addressing the Registers The AD9832 has a serial interface, with 16 bits being loaded during each write cycle. SCLK, SDATA, and FSYNC are used to load the word into the AD9832. A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 When FSYNC is taken low, the AD9832 is informed that a word is being written to the device.
Data Sheet AD9832 When writing to a phase register, the 4 MSBs of the 16-bit word loaded into the data register should be zero (the phase registers are 12 bits wide). Table 10. Controlling the AD9832 D15 1 D14 0 1 1 To alter the entire contents of a frequency register, four write operations are needed. However, the 16 MSBs of a frequency word are contained in a separate register to the 16 LSBs. Therefore, the 16 MSBs of the frequency word can be altered independent of the 16 LSBs. Table 9.
AD9832 Data Sheet Table 11. Writing to the AD9832 Data Registers D15 C3 1 D14 C2 D13 C1 D12 C0 D11 A3 D10 A2 D9 A1 D8 A0 D7 MSB D6 X1 D5 X1 D4 X1 D3 X1 D2 X1 D1 X1 D0 LSB X = don’t care. Table 12. Setting SYNC and SELSRC D15 1 1 D14 0 D13 SYNC D12 SELSRC D11 X1 D10 X1 D9 X1 D8 X1 D7 X1 D6 X1 D5 X1 D4 X1 D3 X1 D2 X1 D1 X1 D0 X1 D9 X1 D8 X1 D7 X1 D6 X1 D5 X1 D4 X1 D3 X1 D2 X1 D1 X1 D0 X1 X = don’t care. Table 13.
Data Sheet AD9832 DATA WRITE FREG[0] = fOUT0/fMCLK × 232 FREG[1] = fOUT1/fMCLK × 232 PHASEREG [3:0] = DELTA PHASE[0, 1, 2, 3] SELECT DATA SOURCES SET FSELECT SET PSEL0, PSEL1 INITIALIZATION WAIT 6 MCLK CYCLES (8 MCLK CYCLES IF SYNC = 1) DAC OUTPUT VOUT = VREFIN × 6.25 × ROUT/RSET × (1 + SIN(2π(FREG × fMCLK × t/232 + PHASEREG/212))) CHANGE PHASE? YES NO NO CHANGE fOUT? YES CHANGE fOUT? CHANGE PHASEREG? YES NO CHANGE PSEL0, PSEL1 09090-024 NO YES Figure 24.
AD9832 Data Sheet DATA WRITE DEFERRED TRANSFER WRITE WRITE 8 BITS TO DEFER REGISTER DIRECT TRANSFER WRITE WRITE PRESENT 8 BITS AND 8 BITS IN DEFER REGISTER TO DATA REGISTER CHANGE 16 BITS YES WRITE ANOTHER WORD TO THIS YES REGISTER? NO CHANGE 8 BITS ONLY 09090-026 NO WRITE A WORD TO ANOTHER REGISTER Figure 26. Data Writes SELECT DATA SOURCES NO YES SELSRC = 0 SET PINS SET FSELECT SET PSEL0 SET PSEL1 SELSRC = 1 FREQUENCY/PHASE REGISTER WRITE SET FSELECT SET PSEL0 SET PSEL1 Figure 27.
Data Sheet AD9832 APPLICATIONS INFORMATION The AD9832 has four phase registers; this enables the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount which is related to the bit stream being input to the modulator. The presence of four shift registers eases the interaction needed between the DSP and the AD9832. The AD9832 is also suitable for signal generator applications.
AD9832 Data Sheet Figure 29 shows the serial interface between the AD9832 and the 68HC11/68L11 microcontroller. The microcontroller is configured as the master by setting bit MSTR in the SPCR to 1, which provides a serial clock on SCK while the MOSI output drives the serial data line SDATA. Because the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7).
Data Sheet AD9832 EVALUATION BOARD SYSTEM DEMONSTRATION PLATFORM The system demonstration platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Blackfin® BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. Note that the SDP board is sold separately from the AD9832 evaluation board.
AD9832 Data Sheet EVALUATION BOARD SCHEMATICS 09090-034 Figure 34. AD9832 Evaluation Board Schematic, Part A Rev.
Data Sheet AD9832 09090-035 Figure 35. AD9832 Evaluation Board Schematic, Part B—J1 Header Connector Rev.
AD9832 Data Sheet 09090-036 EVALUATION BOARD LAYOUT 09090-037 Figure 36. AD9832 Evaluation Board Component Side 09090-038 Figure 37. AD9832 Evaluation Board Silkscreen Figure 38. AD9832 Evaluation Board Solder Side Rev.
Data Sheet AD9832 ORDERING INFORMATION BILL OF MATERIALS Table 14. Reference Designator C1, C3, C5, C6, C11, C12, C13 C7 C2, C4 C8,C9 C10 CLK 1, FSEL1, IOUT, PSEL11, REFIN, PSEL01 FSYNC, IOUT_, MCLK , SCLK, SDATA G2 J1 J2, J3 LK3, LK5, LK6 LK1 R71, R81, R91 R121 R14 R15 R17,R18 R1, R21, R3, R41, R61, R5, R111, R10,R162 R13 U4 U1 U5 Y2 Description 0.1 µF, ±10%, 50 V, X7R, ceramic capacitor 0.
AD9832 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 39.
Data Sheet AD9832 NOTES Rev.
AD9832 Data Sheet NOTES ©1999–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09090-0-2/13(E) Rev.
