Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9833BRMZ

Low Power, 12.65 mW, 2.3 V to 5.5 V,

Programmable Waveform Generator

Data Sheet

AD9833

Rev. E Document Feedback

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FEATURES

Digitally programmable frequency and phase

12.65 mW power consumption at 3 V

0 MHz to 12.5 MHz output frequency range

28-bit resolution: 0.1 Hz at 25 MHz reference clock

Sinusoidal, triangular, and square wave outputs

2.3 V to 5.5 V power supply

No external components required

3-wire SPI interface

Extended temperature range: −40°C to +105°C

Power-down option

10-lead MSOP package

Qualified for automotive applications

APPLICATIONS

Frequency stimulus/waveform generation

Liquid and gas flow measurement

Sensory applications: proximity, motion,

and defect detection

Line loss/attenuation

Test and medical equipment

Sweep/clock generators

Time domain reflectometry (TDR) applications

GENERAL DESCRIPTION

The AD9833 is a low power, programmable waveform generator

capable of producing sine, triangular, and square wave outputs.

Waveform generation is required in various types of sensing,

actuation, and time domain reflectometry (TDR) applications.

The output frequency and phase are software programmable,

allowing easy tuning. No external components are needed. The

frequency registers are 28 bits wide: with a 25 MHz clock rate,

resolution of 0.1 Hz can be achieved; with a 1 MHz clock rate,

the AD9833 can be tuned to 0.004 Hz resolution.

The AD9833 is written to via a 3-wire serial interface. This serial

interface operates at clock rates up to 40 MHz and is compatible

with DSP and microcontroller standards. The device operates

with a power supply from 2.3 V to 5.5 V.

The AD9833 has a power-down function (SLEEP). This function

allows sections of the device that are not being used to be powered

down, thus minimizing the current consumption of the part. For

example, the DAC can be powered down when a clock output is

being generated.

The AD9833 is available in a 10-lead MSOP package.

FUNCTIONAL BLOCK DIAGRAM

SERIAL INTERFACE

AND

CONTROL LOGIC

SCLK S

DAT

FSYNC

CONTR

OL REGISTER

PHASE1 REG

PHASE0 REG

MUX

SIN

ROM

10-BIT DAC

MUX

FREQ0 REG

FREQ1 REG

ON-BOARD

REFERENCE

AGND

DGND

VDD

AD9833

PHASE

ACCUMULATOR

(28-BIT)

REGULA

TOR

CAP/2.5V

2.5V

AVDD/

DVDD

MUX

DIVIDE

BY 2

MSB

MUX

FULL-SCALE

CONTROL

COMP

VOUT

200Ω

MCLK

02704-001

Figure 1.

Summary of content (24 pages)

PAGE 1
Low Power, 12.65 mW, 2.3 V to 5.5 V, Programmable Waveform Generator AD9833 Data Sheet FEATURES GENERAL DESCRIPTION Digitally programmable frequency and phase 12.65 mW power consumption at 3 V 0 MHz to 12.5 MHz output frequency range 28-bit resolution: 0.1 Hz at 25 MHz reference clock Sinusoidal, triangular, and square wave outputs 2.3 V to 5.
PAGE 2
AD9833 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Control Register ......................................................................... 13 Applications ....................................................................................... 1 Frequency and Phase Registers ................................................ 15 General Description .................................................................
PAGE 3
Data Sheet AD9833 SPECIFICATIONS VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ for VOUT, unless otherwise noted. Table 1.
PAGE 4
AD9833 Data Sheet TIMING CHARACTERISTICS VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted. 1 Table 2.
PAGE 5
Data Sheet AD9833 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to AGND VDD to DGND AGND to DGND CAP/2.5V Digital I/O Voltage to DGND Analog I/O Voltage to AGND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature MSOP Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +0.3 V 2.75 V −0.3 V to VDD + 0.
PAGE 6
AD9833 Data Sheet 10 VOUT AD9833 9 AGND TOP VIEW (Not to Scale) 8 FSYNC COMP 1 VDD 2 CAP/2.5V 3 DGND 4 MCLK 5 7 SCLK 6 SDATA 02704-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic COMP VDD 3 CAP/2.5V 4 5 DGND MCLK 6 7 8 SDATA SCLK FSYNC 9 10 AGND VOUT Description DAC Bias Pin. This pin is used for decoupling the DAC bias voltage. Positive Power Supply for the Analog and Digital Interface Sections.
PAGE 7
Data Sheet AD9833 TYPICAL PERFORMANCE CHARACTERISTICS –40 5.5 VDD = 3V TA = 25°C TA = 25°C –45 5.0 VDD = 5V SFDR (dBc) –50 VDD = 3V 4.0 MCLK/7 –55 –60 3.5 MCLK/50 –65 0 5 10 15 MCLK FREQUENCY (MHz) 20 –70 02704-006 3.0 25 5 7 Figure 6. Typical Current Consumption (IDD) vs. MCLK Frequency for fOUT = MCLK/10 6 9 11 13 15 17 19 MCLK FREQUENCY (MHz) 21 23 25 02704-009 IDD (mA) 4.5 Figure 9. Wideband SFDR vs.
PAGE 8
AD9833 Data Sheet 1000 0 950 –10 –20 900 VDD = 2.3V –30 750 VDD = 5.5V 700 –40 –50 –60 650 –70 600 –80 550 –90 500 –40 25 TEMPERATURE (°C) 105 –100 Figure 12. Wake-Up Time vs. Temperature 0 RWB 1k VWB 300 FREQUENCY (Hz) 5M ST 50 SEC 02704-015 POWER (dB) 800 02704-012 WAKE-UP TIME (µs) 850 Figure 15. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 1.43 MHz = fMCLK/7, Frequency Word = 0x2492492 0 1.250 –10 1.225 –20 UPPER RANGE –30 POWER (dB) VREF (V) 1.200 1.
PAGE 9
AD9833 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –60 –70 –80 –80 –90 –90 –100 VWB 100 FREQUENCY (Hz) 1M ST 100 SEC –10 –10 –20 –20 –30 –30 POWER (dB) 0 –40 –50 –60 –50 –60 –70 –80 –80 –90 –90 –100 02704-019 –100 12.5M ST 100 SEC Figure 19. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 600 kHz, Frequency Word = 0x0624DD3 –10 –20 –30 –40 –50 –60 –70 –80 VWB 300 FREQUENCY (Hz) 12.5M ST 100 SEC 02704-020 –90 0 RWB 1k 0 RWB 1k VWB 300 FREQUENCY (Hz) 12.5M ST 100 SEC Figure 22.
PAGE 10
AD9833 Data Sheet TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 … 00 to 000 … 01), and full scale, a point 0.5 LSB above the last code transition (111 … 10 to 111 … 11). The error is expressed in LSBs.
PAGE 11
Data Sheet AD9833 THEORY OF OPERATION Sine waves are typically thought of in terms of their magnitude form: a(t) = sin(ωt). However, these sine waves are nonlinear and not easy to generate except through piecewise construction. On the other hand, the angular information is linear in nature. That is, the phase angle rotates through a fixed angle for each unit of time. The angular rate depends on the frequency of the signal by the traditional rate of ω = 2πf.
PAGE 12
AD9833 Data Sheet CIRCUIT DESCRIPTION The AD9833 is a fully integrated direct digital synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor, and decoupling capacitors to provide digitally created sine waves up to 12.5 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes.
PAGE 13
Data Sheet AD9833 FUNCTIONAL DESCRIPTION SERIAL INTERFACE To avoid spurious DAC outputs during AD9833 initialization, the reset bit should be set to 1 until the part is ready to begin generating an output. A reset does not reset the phase, frequency, or control registers. These registers will contain invalid data and, therefore, should be set to known values by the user. The reset bit should then be set to 0 to begin generating an output.
PAGE 14
AD9833 Data Sheet Table 6. Description of Bits in the Control Register Bit D13 Name B28 D12 HLB D11 D10 FSELECT PSELECT D9 D8 Reserved Reset D7 SLEEP1 D6 SLEEP12 D5 OPBITEN D4 D3 Reserved DIV2 D2 D1 Reserved Mode D0 Reserved Function Two write operations are required to load a complete word into either of the frequency registers. B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes.
PAGE 15
Data Sheet AD9833 FREQUENCY AND PHASE REGISTERS Table 9. Writing 0xFFFC000 to the FREQ0 Register The AD9833 contains two frequency registers and two phase registers, which are described in Table 7. SDATA Input 0010 0000 0000 0000 Table 7. Frequency and Phase Registers Register FREQ0 Size 28 bits FREQ1 28 bits PHASE0 12 bits PHASE1 12 bits Description Frequency Register 0. When the FSELECT bit = 0, this register defines the output frequency as a fraction of the MCLK frequency.
PAGE 16
AD9833 Data Sheet RESET FUNCTION VOUT PIN The reset function resets appropriate internal registers to 0 to provide an analog output of midscale. Reset does not reset the phase, frequency, or control registers. When the AD9833 is powered up, the part should be reset. To reset the AD9833, set the reset bit to 1. To take the part out of reset, set the bit to 0. A signal appears at the DAC to output eight MCLK cycles after reset is set to 0.
PAGE 17
Data Sheet AD9833 APPLICATIONS INFORMATION Because of the various output options available from the part, the AD9833 can be configured to suit a wide variety of applications. One of the areas where the AD9833 is suitable is in modulation applications. The part can be used to perform simple modulation, such as FSK. More complex modulation schemes, such as GMSK and QPSK, can also be implemented using the AD9833.
PAGE 18
AD9833 Data Sheet DATA WRITE (SEE FIGURE 28) SELECT DATA SOURCES WAIT 7/8 MCLK CYCLES INITIALIZATION (SEE FIGURE 27 BELOW) DAC OUTPUT VOUT = VREF × 18 × RLOAD / RSET × (1 + (SIN (2π (FREQREG × fMCLK × t/228 + PHASEREG / 212)))) YES CHANGE PSELECT? CHANGE PHASE? NO YES CHANGE FSELECT? CHANGE PHASE REGISTER? CHANGE FREQUENCY? YES NO NO CHANGE FREQUENCY REGISTER? CHANGE DAC OUTPUT FROM SIN TO RAMP? YES NO CONTROL REGISTER WRITE (SEE TABLE 6) YES CHANGE OUTPUT TO A DIGITAL SIGNAL? 02704-026
PAGE 19
Data Sheet AD9833 DATA WRITE WRITE A FULL 28-BIT WORD TO A FREQUENCY REGISTER? YES (CONTROL REGISTER WRITE) B28 (D13) = 1 NO WRITE 14MSBs OR LSBs TO A FREQUENCY REGISTER? NO WRITE TO PHASE REGISTER? YES YES (CONTROL REGISTER WRITE) B28 (D13) = 0 HLB (D12) = 0/1 (16-BIT WRITE) YES WRITE A 16-BIT WORD (SEE TABLE 9 FOR EXAMPLE) (SEE TABLE 10 AND TABLE 11 FOR EXAMPLES) WRITE ANOTHER FULL 28-BIT WORD TO A FREQUENCY REGISTER? WRITE 14MSBs OR LSBs TO A FREQUENCY REGISTER? NO YES NO Figure 28.
PAGE 20
AD9833 Data Sheet INTERFACING TO MICROPROCESSORS AD9833 TO 68HC11/68L11 INTERFACE Figure 29 shows the serial interface between the AD9833 and the 68HC11/68L11 microcontroller. The microcontroller is configured as the master by setting the MSTR bit in the SPCR to 1. This setting provides a serial clock on SCK; the MOSI output drives the serial data line SDATA. Because the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7).
PAGE 21
Data Sheet AD9833 EVALUATION BOARD The AD9833 evaluation board allows designers to evaluate the high performance AD9833 DDS modulator with a minimum of effort. More information about the evaluation software is available on the software CD and on the AD9833 product page. SYSTEM DEMONSTRATION PLATFORM The system demonstration platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards.
PAGE 22
AD9833 Data Sheet 02704-036 EVALUATION BOARD SCHEMATICS 02704-037 Figure 34. Evaluation Board Schematic Figure 35. SDP Connector Schematic Rev.
PAGE 23
Data Sheet AD9833 02704-038 02704-040 EVALUATION BOARD LAYOUT Figure 38. AD9833 Evaluation Board Solder Side 02704-039 Figure 36. AD9833 Evaluation Board Component Side Figure 37. AD9833 Evaluation Board Silkscreen Rev.
PAGE 24
AD9833 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 39.