Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9847AKSTZ

REV. A

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AD9847

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

10-Bit 40 MSPS CCD Signal Processor

with Integrated Timing Driver

FUNCTIONAL BLOCK DIAGRAM

CLAMP

DOUT

CCDIN

PBLK

VRT

VRB

INTERNAL

REGISTERS

2dB TO 36dB

SYNC

GENERATOR

SDATASCK

CLPOB

VGA

AD9847

4  6dB

PRECISION

TIMING

CORE

ADC

VREF

CLAMP

INTERNAL

CLOCKS

PxGA

CDS

HORIZONTAL

DRIVERS

H1–H4

HD VD

CLI

CLPDM

GENERAL DESCRIPTION

The AD9847 is a highly integrated CCD signal processor for

digital still camera applications. The AD9847 includes a com-

plete analog front end with A/D conversion, combined with

a programmable timing driver. The Precision Timing core allows

adjustment of high speed clocks with approximately 500 ps

resolution at clock speeds of 40 MHz.

The AD9847 is specified at pixel rates of 40 MHz. The analog

front end includes black level clamping, CDS, PxGA, VGA, and a

10-bit A/D converter. The timing driver provides the high speed

CCD clock drivers for RG and H1–H4. Operation is programmed

using a 3-wire serial interface.

Packaged in a space-saving 48-lead LQFP, the AD9847 is speci-

fied over an operating temperature range of –20°C to +85°C.

FEATURES

Correlated Double Sampler (CDS)

–2 dB to +10 dB Pixel Gain Amplifier (

PxGA

)

2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)

10-Bit 40 MHz A/D Converter

Black Level Clamp with Variable Level Control

Complete On-Chip Timing Driver

Precision Timing

™ Core with 500 ps

Resolution at 40 MSPS

On-Chip 5 V Horizontal and RG Drivers

48-Lead LQFP Package

APPLICATIONS

Digital Still Cameras

Summary of content (28 pages)

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a 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver AD9847 FEATURES Correlated Double Sampler (CDS) –2 dB to +10 dB Pixel Gain Amplifier (PxGA®) 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) 10-Bit 40 MHz A/D Converter Black Level Clamp with Variable Level Control Complete On-Chip Timing Driver Precision Timing™ Core with 500 ps Resolution at 40 MSPS On-Chip 5 V Horizontal and RG Drivers 48-Lead LQFP Package GENERAL DESCRIPTION The AD9847 is a highly integrated CCD signal processor
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AD9847–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter Min TEMPERATURE RANGE Operating Storage –20 –65 MAXIMUM CLOCK RATE 40 POWER SUPPLY VOLTAGE Analog (AVDD1, 2, 3) Digital1 (DVDD1) H1–H4 Digital2 (DVDD2) RG Digital3 (DVDD3) D0–D11 Digital4 (DVDD4) All Other Digital Typ Unit +85 +150 °C °C MHz 2.7 3.0 3.
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AD9847 ANALOG SPECIFICATIONS (T MIN Parameter to TMAX, AVDD = DVDD = 3.0 V, fCLI = 40 MHz, unless otherwise noted.
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AD9847 TIMING SPECIFICATIONS (C to 29 pF, f L Parameter MASTER CLOCK (CLI) CLI Clock Period CLI High/Low Pulsewidth Delay from CLI to Internal Pixel Period Position CLI = 40 MHz, Serial Timing in Figures 3a and 3b, unless otherwise noted.) Symbol Min tCLI tADC 25 12.
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AD9847 ABSOLUTE MAXIMUM RATINGS AVDD1, 2, 3 to AVSS . . . . . . . . . . . . . . . . . . . –0.3 to +3.9 V DVDD1, 2 to DVSS . . . . . . . . . . . . . . . . . . . . –0.3 to +5.5 V DVDD3, 4 to DVSS . . . . . . . . . . . . . . . . . . . . –0.3 to +3.9 V Digital Outputs to DVSS3 . . . . . . . . –0.3 to DVDD3 + 0.3 V CLPOB, CLPDM, BLK to DVSS4 . –0.3 to DVDD4 + 0.3 V CLI to AVSS . . . . . . . . . . . . . . . . . . . –0.3 to AVDD + 0.3 V SCK, SL, SDATA to DVSS4 . . . . . –0.3 to DVDD4 + 0.3 V VRT, VRB to AVSS . .
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AD9847 SDI SCK CLPOB CLPDM HBLK PBLK VD HD DVSS4 DVDD4 NC NC PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 (LSB) D0 1 PIN 1 IDENTIFIER D1 2 D2 3 D3 4 D4 5 DVSS3 6 AD9847 TOP VIEW (Not to Scale) DVDD3 7 D5 8 36 SL 35 REFT 34 REFB 33 CMLEVEL 32 AVSS3 31 AVDD3 30 BYP3 29 CCDIN D6 9 D7 10 28 BYP2 BYP1 26 AVDD2 27 D8 11 (MSB) D9 12 25 AVSS2 AVDD1 CLI AVSS1 DVDD2 RG DVSS2 H4 H3 DVDD1 DVSS1 NC = NO CONNECT H2 H1 13 14 15 16 17 18 19 20 21 22 23 24 PIN F
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AD9847 Equivalent Input/Output Circuits AVDD2 DVDD4 R 330 AVSS2 AVSS2 DVSS4 Circuit 1. CCDIN (Pin 29) Circuit 4. Digital Inputs (Pins 36–44) AVDD1 DVDD1 DATA 330 25k CLI 1.4V ENABLE OUTPUT AVSS1 Circuit 2. CLI (Pin 23) DVDD4 DVSS1 DVDD3 Circuit 5. H1–H4 and RG (Pins 13, 14, 17, 18, 20) DATA THREESTATE DOUT DVSS4 DVSS3 Circuit 3. Data Outputs D0–D9 (Pins 1–5, 8–12) Typical Performance Characteristics 4 0.25 3 OUTPUT NOISE – LSB 0.50 0 –0.25 2 1 –0.
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AD9847 SYSTEM OVERVIEW V-DRIVER Figures 1a and 1b show the typical system application diagrams for the AD9847. The CCD output is processed by the AD9847’s AFE circuitry, which consists of a CDS, PxGA, VGA, black level clamp, and A/D converter. The digitized pixel information is sent to the digital image processor chip, where all post-processing and compression occurs. To operate the CCD, CCD timing parameters are programmed into the AD9847 from the image processor through the 3-wire serial interface.
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AD9847 SERIAL INTERFACE TIMING SDATA A0 A1 A2 A3 t DS A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 XX XX t DH SCK t LS t LH SL SL UPDATED VD/HD UPDATED VD HD NOTES 1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. 2. 14 SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS. 3. FOR 16-BIT SYSTEMS, TWO EXTRA DUMMY BITS MAY BE WRITTEN. DUMMY BITS ARE IGNORED. 4. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE. 5.
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AD9847 clpdmscp3 register, the contents of Address 0x81 must be written first, followed by the contents of Address 0x82. The register will be updated after the completion of the write to Register 0x82, either at the next SL rising edge or the next VD/HD falling edge. Accessing a Double-Wide Register There are many double-wide registers in the AD9847, e.g., oprmode, clpdmtog1_0, and clpdmscp3, and so on.
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AD9847 Address Bit Content Width Default Value Register Name Register Description 1 1 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 0 2 6 6 2 6 6 2 6 6 2 01 00 01 2C 00 35 00 01 3E 02 16 03 00 3F 3F 3F 3F 01 3F 3F 3F 3F 00 00 3F 3F 00 3F 3F 00 3F 3F 00 clpdmdir clpdmpol clpdmspol0 clpdmtog1_0[5:0] clpdmtog1_0[11:6] clpdmtog2_0[5:0] clpdmtog2_0[11:6] clpdmspol1 clpdmtog1_1[5:0] clpdmtog1_1[11:6] clpdmtog2_1[5:0] clpdmtog2_1[11:6] clpdmspol2 clpdmtog1_2[5:0] clpdmtog1_2[11:6] clpdmtog2_2[5:0] clpdmtog2_2[11
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AD9847 Address Bit Content Width Default Value Register Name Register Description 1 1 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 0 2 6 6 2 6 6 2 6 6 2 01 00 01 0E 00 2B 00 01 2B 06 3F 3F 00 3F 3F 3F 3F 01 3F 3F 3F 3F 00 03 01 00 01 02 00 00 37 03 03 clpobdir clpobpol clpobpol0 clpobtog1_0[5:0] clpobtog1_0[11:6] clpobtog2_0[5:0] clpobtog2_0[11:6] clpobpol1 clpobtog1_1[5:0] clpobtog1_1[11:6] clpobtog2_1[5:0] clpobtog2_1[11:6] clpobspol2 clpobtog1_2[5:0] clpobtog1_2[11:6] clpobtog2_2[5:0] clpobtog2_2[11:6
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AD9847 Address Bit Content Width Default Value Register Name Register Description HBLK # Bits 147 A4 A5 A6 [0] [0] [0] 1 1 1 01 00 01 hblkdir hblkpol hblkextmask A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] BB BC BD BE BF C0 C1 C2 C3 C4 [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 0 2 6 6 2 6 6 2 6 6 2 01 3E 00 0D
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AD9847 Address Bit Content Width Default Value Register Name Register Description 1 1 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 0 2 6 6 2 6 6 2 6 6 2 01 00 01 3D 00 2A 06 00 2A 06 3F 3F 00 3F 3F 3F 3F 01 3F 3F 3F 3F 00 02 01 00 01 02 00 00 37 03 02 pblkdir pblkpol pblkspol0 pblktog1_0[5:0] pblktog1_0[11:6] pblkbtog2_0[5:0] pblkbtog2_0[11:6] pblkspol1 pblktog1_1[5:0] pblktog1_1[11:6] pblktog2_1[5:0] pblktog2_1[11:6] pblkspol2 pblktog1_2[5:0] pblktog1_2[11:6] pblktog2_2[5:0] pblktog2_2[11:6] pblkspol3 p
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AD9847 Address Bit Content Width Default Value Register Name Register Description AFE Register Breakdown oprmode [7:0] Serial Address: 8'h00 {oprmode[5:0]}, 8'h01 {oprmode[7:6]} 8'h0 [1:0] 2'h0 2'h1 2'h2 2'h3 powerdown[1:0] [2] [3] [4] [5] [6] [7] ctlmode disblack test mode test mode test mode test mode test mode [5:0] 6'h0 [2:0] Serial Address: 8'h06 {cltmode[5:0]} 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 [3] [4] ctlmode[2:0] tristateout PRECISION TIMING HIGH SPEED TIMING GENERATION
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AD9847 High Speed Clock Programmability Figure 5 shows how the high speed clocks RG, H1–H4, SHP, and SHD are generated. The RG pulse has programmable rising and falling edges and may be inverted using the polarity control. The horizontal clocks H1 and H3 have programmable rising and falling edges and polarity control. The H2 and H4 clocks are always inverses of H1 and H3, respectively. Table II summarizes the high speed timing registers and their parameters.
PAGE 17
AD9847 POSITION P[0] P[24] P[12] P[48] = P[0] P[36] PIXEL PERIOD RGf[12] RGr[0] RG Hf[24] Hr[0] H1/H3 SHP[28] SHD[48] tS1 CCD SIGNAL NOTES 1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. 2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN ABOVE. Figure 6. High Speed Clock Default and Programmable Locations H-Driver and RG Outputs In addition to the programmable timing positions, the AD9847 features on-chip output drivers for the RG and H1–H4 outputs.
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AD9847 HORIZONTAL CLAMPING AND BLANKING The AD9847’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. As with the vertical timing generation, individual sequences are defined for each signal and are then organized into multiple regions during image readout. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout, in order to accommodate different image transfer timing and high speed line shifts.
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AD9847 ... HD ... HBLK H1/H3 THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1) ... H1/H3 H2/H4 ... Figure 11. HBLK Masking Control Horizontal Sequence Control The AD9847 uses sequence change positions (SCP) and sequence pointers (SPTR) to organize the individual horizontal sequences. Up to four SCPs are available to divide the readout into four separate regions, as shown in Figure 12. The SCP 0 is always hard-coded to line 0, and SCP1–3 are register programmable.
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AD9847 circuitry by first writing “110101” or “53” decimal to the INITIAL1 Register (Address x020). Finally, write “000100” or “4” decimal to the INITIAL2 Register (Address x00F). H-Counter Synchronization The H-Counter reset occurs on the sixth CLI rising edge following the HD falling edge. The PxGA steering is synchronized with the reset of the internal H-Counter (see Figure 13). 4. Write a “1” to the PREVENTUPDATE Register (Address x019). This will prevent the updating of the serial register data.
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AD9847 Another advantage of removing this offset at the input stage is to maximize system headroom. Some area CCDs have large black level offset voltages, which, if not corrected at the input stage, can significantly reduce the available headroom in the internal circuitry when higher VGA gain settings are used. ANALOG FRONT END DESCRIPTION AND OPERATION The AD9847 signal processing chain is shown in Figure 15. Each processing step is essential in achieving a high quality image from the raw CCD pixel data.
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AD9847 ODD FIELD FLD EVEN FIELD VD HD PxGA GAIN REGISTER X X 0 1 0 1 2 3 2 3 0 1 0 1 0 1 0 1 2 3 2 3 0 1 0 1 0 2 3 2 3 0 0 1 0 1 0 0 1 2 0 0 NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE. 2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “0101” AND “2323” LINES. 3. FLD STATUS IS IGNORED. Figure 16a.
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AD9847 ODD FIELD FLD EVEN FIELD VD HD PxGA GAIN REGISTER X X 0 1 2 0 2 1 0 2 0 1 2 0 0 1 2 0 2 1 0 2 0 1 2 0 0 0 1 2 3 0 0 1 2 3 0 NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “012012” LINE. 2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER, STEERING BETWEEN “012012” AND “210210” LINES. 3. FLD STATUS IS IGNORED. Figure 16e.
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AD9847 VD COLOR STEERING CONTROL HD SHP/SHD 3 PxGA STEERING MODE SELECTION 10 CONTROL REGISTER BITS D0–D2 8 2 GAIN1 4:1 MUX GAIN2 PxGA CDS PxGA GAIN REGISTERS GAIN3 6 6 PxGA GAIN – dB GAIN0 4 2 VGA 0 Figure 17. PxGA Block Diagram CCD: PROGRESSIVE BAYER –2 32 (100000) MOSAIC SEPARATE COLOR STEERING MODE R Gr R Gr LINE0 GAIN0, GAIN1, GAIN0, GAIN1... Gb B Gb B LINE1 GAIN2, GAIN3, GAIN2, GAIN3... R Gr R Gr LINE2 GAIN0, GAIN1, GAIN0, GAIN1...
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AD9847 Optical Black Clamp APPLICATIONS INFORMATION External Circuit Configuration The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD’s black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a fixed black level reference, selected by the user in the clamp level register. The value can be programmed between 0 LSB and 63.75 LSB with 8-bit resolution.
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AD9847 CCDIN 29 AD9847 AD9847 ASIC 17 18 H3 H4 13 H1 14 20 H2 LPF 23 RG CLI 1nF MASTER CLOCK SIGNAL OUT Figure 23b. CLI Connection, AC-Coupled H2 H1 RG Internal Mode Circuit Configuration CCD IMAGER The AD9847 may be used in internal mode using the circuit configuration of Figure 24. Internal mode uses the same circuit as Figure 21, except that the horizontal pulses (CLPOB, CLPDM, PBLK, and HBLK) are internally generated in the AD9847.
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AD9847 Timing Examples (continued) CCDIN INVALID PIXELS VERT SHIFT DUMMY INVALID PIXELS VERT SHIFT SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM Figure 26. Sequence 1: Vertical Blanking EFF. PIXELS OPTICAL BLACK VERT SHIFT DUMMY CCDIN OPTICAL BLACK VERT SHIFT SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM Figure 27. Sequence 2: Vertical Optical Black EFF. PIXELS CCDIN OPTICAL BLACK VERT SHIFT DUMMY OB EFFECTIVE PIXELS SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM Figure 28.
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AD9847 OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.4 mm Thick (ST-48) 1.60 MAX 0.75 0.60 0.45 PIN 1 INDICATOR 9.00 BSC 37 48 36 1 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 SEATING PLANE C02626–0–1/03(A) Dimensions shown in millimeters 7.00 BSC TOP VIEW (PINS DOWN) 7 3.5 0 0.08 MAX COPLANARITY VIEW A 25 12 13 0.50 BSC VIEW A ROTATED 90 CCW 24 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026BBC Revision History Location Page 1/03—Data Sheet changed from REV.