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AD9851

CMOS 180 MHz

DDS/DAC Synthesizer

FEATURES

180 MHz Clock Rate with Selectable 6



Reference Clock

Multiplier

On-Chip High Performance 10-Bit DAC and High Speed

Comparator with Hysteresis

SFDR >43 dB @ 70 MHz A

OUT

32-Bit Frequency Tuning Word

Simpli ed Control Interface: Parallel or Serial

Asynchronous Loading Format

5-Bit Phase Modulation and Offset Capability

Comparator Jitter <80 ps p-p @ 20 MHz

2.7 V to 5.25 V Single-Supply Operation

Low Power: 555 mW @ 180 MHz

Power-Down Function, 4 mW @ 2.7 V

Ultrasmall 28-Lead SSOP Packaging

APPLICATIONS

Frequency/Phase-Agile Sine Wave Synthesis

Clock Recovery and Locking Circuitry for Digital

Communications

Digitally Controlled ADC Encode Generator

Agile Local Oscillator Applications in Communications

Quadrature Oscillator

CW, AM, FM, FSK, MSK Mode Transmitter

FUNCTIONAL BLOCK DIAGRAM

32-BIT

TUNING

WORD

PHASE

AND

CONTROL

WORDS

FREQUENCY/PHASE

DATA REGISTER

DATA INPUT REGISTER

10-BIT

DAC

DAC R

SET

ANALOG

OUT

ANALOG

CLOCK OUT

HIGH SPEED

DDS

FREQUENCY

UPDATE/DATA

RESET

WORD LOAD

CLOCK

MASTER

RESET

REF

CLOCK IN

6 REFCLK

MULTIPLIER

COMPARATOR

SERIAL

LOAD

1 BIT 

40 LOADS

PARALLEL

LOAD

8 BITS 

5 LOADS

FREQUENCY, PHASE

AND CONTROL DATA INPUT

AD9851

GND

GENERAL DESCRIPTION

The AD9851 is a highly integrated device that uses advanced

DDS technology, coupled with an internal high speed, high

performance D/A converter, and comparator, to form a dig i tal ly

programmable frequency synthesizer and clock generator func-

tion. When referenced to an accurate clock source, the AD9851

generates a stable frequency and phase-programmable digitized

analog output sine wave. This sine wave can be used directly as

a frequency source, or internally converted to a square wave for

agile-clock generator applications. The AD9851’s innovative

high speed DDS core accepts a 32-bit frequency tuning word,

which results in an output tuning res o lu tion of approximately

0.04 Hz with a 180 MHz system clock. The AD9851 con tains

a unique 6



REFCLK Multiplier circuit that eliminates the

need for a high speed reference oscillator. The 6



REFCLK

Multiplier has min i mal impact on SFDR and phase noise char-

ac ter is tics. The AD9851 provides  ve bits of programmable

phase mod u la tion resolution to enable phase shifting of its

output in in cre ments of 11.25°.

The AD9851 contains an internal high speed comparator that

can be con gured to accept the (externally)  ltered output of the

DAC to generate a low jitter output pulse.

The frequency tuning, control, and phase modulation words are

asynchronously loaded into the AD9851 via a parallel or serial

loading format. The parallel load format consists of  ve it er a tive

loads of an 8-bit control word (byte). The  rst 8-bit byte controls

output phase, 6



REFCLK Multiplier, power-down enable and

loading for mat; the remaining bytes comprise the 32-bit frequency

tuning word. Serial loading is accomplished via a 40-bit serial data

stream entering through one of the parallel input bus lines. The

AD9851 uses advanced CMOS technology to provide this break-

through level of functionality on just 555 mW of power dissipation

(5 V supply), at the maximum clock rate of 180 MHz.

The AD9851 is available in a space-saving 28-lead SSOP,

surface-mount package that is pin-for-pin compatible with the

popular AD9850 125 MHz DDS. It is speci ed to operate over

the extended industrial temperature range of –40°C to +85°C

at >3.0 V supply voltage. Below 3.0 V, the speci cations apply

over the commercial temperature range of 0°C to 85°C.

REV. D

Summary of content (24 pages)

PAGE 1
CMOS 180 MHz DDS/DAC Synthesizer AD9851 FEATURES 180 MHz Clock Rate with Selectable 6 Reference Clock Multiplier On-Chip High Performance 10-Bit DAC and High Speed Comparator with Hysteresis SFDR >43 dB @ 70 MHz AOUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel or Serial Asynchronous Loading Format 5-Bit Phase Modulation and Offset Capability Comparator Jitter <80 ps p-p @ 20 MHz 2.7 V to 5.25 V Single-Supply Operation Low Power: 555 mW @ 180 MHz Power-Down Function, 4 mW @ 2.
PAGE 2
AD9851–SPECIFICATIONS (VS1 = 5 V  5%, RSET = 3.9 k, 6 REFCLK Multiplier Disabled, External Reference Clock = 180 MHz, except as noted.) Parameter Temp Level Min Full Full 0°C to 85°C IV IV IV Full Full 0°C to 85°C Full Full 25°C Test AD9851BRS Max Unit 1 1 1 180 125 100 MHz MHz MHz IV IV IV IV IV V 5 5 5 45 35 30 20.83 16.66 60 65 MHz MHz MHz % % M 25°C 25°C 25°C 25°C IV IV IV IV 3.5 2.3 25°C 25°C 25°C 25°C 25°C IV I I I I 5 –10 25°C 25°C 25°C 25°C V V V I –0.
PAGE 3
AD9851 Temp Test Level Min Full Full Full Full Full IV IV IV IV IV 3.5 3.5 7 3.5 7 ns ns ns ns ns Full IV 18 Full IV 13 tRH (CLKIN Delay After RESET Rising Edge) tRL (RESET Falling Edge After CLKIN) tRR (Recovery from RESET) Full Full Full IV IV IV 3.5 3.
PAGE 4
AD9851 ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS Test Level Maximum Junction Temperature . . . . . . . . . . . . . . . . . . .150°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Operating Temperature . . . . . . . . . . . . . . . . . . . –40°C to +85°C Digital Inputs . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS + 0.7 V Lead Temperature (10 sec) Soldering . . .
PAGE 5
AD9851 PIN CONFIGURATION D3 1 28 D4 D2 2 27 D5 D1 3 26 D6 LSB D0 4 25 D7 MSB/SERIAL LOAD PGND 5 24 DGND PVCC 6 23 DVDD W CLK 7 AD9851 RESET TOP VIEW FQ UD 8 (Not to Scale) 21 IOUT 22 REFCLOCK 9 20 IOUTB AGND 10 19 AGND AVDD 11 18 AVDD RSET 12 17 DACBP VOUTN 13 16 VINP VOUTP 14 15 VINN PIN FUNCTION DESCRIPTIONS Pin No.
PAGE 6
AD9851–Typical Performance Characteristics 0 0 RBW = 5kHz VBW = 5kHz SWT = 7.2s RF ATT = 20dB REF LVL = –7dBm –10 –20 –30 –20 –30 2AP –40 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 0Hz START 7.2MHz/ –100 1.1MHz CENTER 72MHz STOP 200kHz SPAN 0 0 RBW = 5kHz VBW = 5kHz SWT = 7.2s RF ATT = 20dB REF LVL = –7dBm –10 –20 –30 –20 –30 –50 –60 –60 –70 –70 –80 –80 –90 –90 7.2MHz/ 2AP –40 –50 –100 0Hz START RBW = 300Hz VBW = 300Hz SWT = 11.
PAGE 7
AD9851 Tek Run 4.00GS/s Sample T [ Tek Run 4.00GS/s ]  : 208ps @ : 1.940ns Sample [ T ]  : 280ps @ : 2.668ns 1 1 M 12.5ns Ch 1 –200mV D 200ps Runs After Ch1 200mV Ch1 200mV TPC 7. Typical CMOS comparator p-p output jitter with the AD9851 configured as a clock generator, DDS f OUT = 10.1 MHz, VS = 5 V, system clock = 180 MHz, 70 MHz LPF. Graph details the center portion of a rising edge with scope in delayed trigger mode, 200 ps/div. Cursors show 208 ps p-p jitter. Tek Run 4.
PAGE 8
AD9851 Tek Stop 2.50GS/s –120 2227 Acgs T [ ] AD9851 RESIDUAL PHASE NOISE  : 2.3ns @ : 103.6ns MAGNITUDE – –dBc/Hz –125 C1 Fall 2.33ns –130 –135 –140 –145 1 –150 –155 100 1k 10k FREQUENCY OFFSET – Hz 100k TPC 14. Comparator Fall Time, 15 pF Load TPC 11. Output Residual Phase Noise (5.2 MHz AOUT), 6 REFCLK Multiplier Disabled, System Clock = 180 MHz, Reference Clock = 180 MHz 120 75 110 FUNDAMENTAL OUTPUT = SYSTEM CLOCK/3 100 SUPPLY CURRENT – mA 70 SFDR – –dBc 65 VS = +3.
PAGE 9
AD9851 70 600 1.1MHz 500 p-p AMPLITUDE – mV 65 SFDR – –dBc 60 40.1MHz 55 50 400 VS = +3.3V 300 VS = +5V 200 70.1MHz 45 40 100 5 10 15 MAXIMUM DAC IOUT – mA 0 20 TPC 17. Effect of DAC maximum output current on wideband (0 to 72 MHz) SFDR at three representative DAC output frequencies: 1.1 MHz, 40.1 MHz, and 70.1 MHz. VS = 5 V, 180 MHz system clock (6  REFCLK multiplier disabled). Currents are set using appropriate values of RSET. REV.
PAGE 10
AD9851 I/Q MIXER AND LOW-PASS FILTER Rx RF IN 8 I AD9059 DUAL 8-BIT ADC Q VCA AGC ADC CLOCK FREQUENCY LOCKED TO Tx CHIP/SYMBOL/PN RATE 180MHz OR 30MHz ADC ENCODE AD9851 32 CLOCK GENERATOR REFERENCE CLOCK Rx BASEBAND DIGITAL DATA OUT DIGITAL DEMODULATOR 8 CHIP/SYMBOL/PN RATE DATA Figure 1.
PAGE 11
AD9851 W CLK #1 W CLK IOUT AD9851 #1 FQ UD RESET W CLK #1 FQ UD FQ UD MICROPROCESSOR OR MICROCONTROLLER 8-BIT DATA BUS REF CLOCK RESET RESET RESET FQ UD W CLK #2 90 PHASE DIFFERENCE The differential DAC output connection in Figure 9 enables reduction of common-mode signals and allows highly reactive filters to be driven without a filter input termination resistor (see above single-ended example, Figure 8).
PAGE 12
AD9851 REFERENCE CLOCK DDS CIRCUITRY N PHASE ACCUMULATOR AMPLITUDE/SINE CONV ALGORITHM D/A CONVERTER LP COMPARATOR CLOCK OUT TUNING WORD SPECIFIES OUTPUT FREQUENCY AS A FRACTION OF REF CLOCK FREQUENCY IN DIGITAL DOMAIN Figure 11.
PAGE 13
AD9851 In the example shown in Figure 12, the system clock is 100 MHz and the output frequency is set to 20 MHz. As can be seen, the aliased images are very prominent and of a relatively high energy level as determined by the sin(x)/x rolloff of the quantized D/A converter output. In fact, depending on the f/system clock relationship, the first aliased image can equal the fundamental amplitude (when fOUT = 1/2 system clock).
PAGE 14
AD9851 4. Output = 10 MHz (for 180 MHz system clock) the factory test mode. Exit from serial mode to parallel mode is only possible using the RESET command. The function assignments of the data and control words are shown in Tables I and III; the detailed timing sequence for updating the output frequency and/or phase, resetting the device, engaging the 6 REFCLK multiplier, and powering up/down, are shown in the timing diagrams of Figures 13 through 20.
PAGE 15
AD9851 SYSCLK t RL t RH t RR RESET t RS t OL AOUT COS (0 ) SYMBOL tRH tRL tRR tRS tOL DEFINITION MIN SPEC CLK DELAY AFTER RESET RISING EDGE RESET FALLING EDGE AFTER CLK RECOVERY FROM RESET MINIMUM RESET WIDTH RESET OUTPUT LATENCY 3.5ns* 3.5ns* 2 SYSCLK CYCLES 5 SYSCLK CYCLES 13 SYSCLK CYCLES *SPECIFICATIONS DO NOT APPLY WHEN THE REF CLOCK MULTIPLIER IS ENGAGED NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME NEEDED BEFORE WRITING TO THE DEVICE.
PAGE 16
AD9851 DATA W0 W1 W2 W3 W39 FQ UD W CLK 40 W CLK CYCLES Figure 19. Serial Load Frequency/Phase Update Sequence Table III. 40-Bit Serial Load Word Functional Assignment W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W33 W34 W35 W36 W37 W38 W39 Figure 20 shows a normal 40-bit serial word load sequence with W33 always set to Logic 0 and W34 set to Logic 1 or Logic 0 to control the power-down function.
PAGE 17
AD9851 PCB LAYOUT INFORMATION The AD9851/CGPCB and AD9851/FSPCB evaluation boards (Figures 22 through 25 and TPCs 1 and 2) represent typical implementations of the AD9851 and exemplify the use of high frequency/high resolution design and layout practices. The printed circuit board that contains the AD9851 should be a multilayer board that allows dedicated power and ground planes. The power and ground planes should (as much as possible) be free of etched traces that cause discontinuities in the planes.
PAGE 18
AD9851 Apply power to AD9851 evaluation board. The AD9851 is powered separately from the other active components on the board via connector marked DUT +V. The connector marked 5 V is used to power the CMOS latches, optional crystal oscillator and pull-up resistors. Both 5 V and DUT +V may be tied together for ease of operation without adverse affects. The AD9851 may be powered with 2.7 V to 5.25 V. Other operational modes (Frequency Sweeping, Sleep, Serial Input) are available.
PAGE 19
AD9851 J1 C36CPRX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 U2 74HCT574 RRSET 9 8 7 6 5 4 3 2 8D 7D 6D 5D 4D 3D 2D 1D CK 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 12 13 14 15 16 17 18 19 AD9851/FSPCB FREQUENCY SYNTHESIZER EVALUATION BOARD D0 D1 D2 D3 D4 D5 D6 D7 D4 28 D4 D2 2 D2 D5 27 D5 U1 AD9851 D1 3 D1 D7 25 D7 GND 5 PGND RESET 22 RESET FQUD 8 FQ UD J6 IOUT 21 CLKIN 9 REFCLOCK IOUTB 20 GND 10 AGND 10mA RESET U3 74HCT574 RRESET WWCLK FFQUD RRESET
PAGE 20
AD9851 23a. FSPCB Top Layer 23c. FSPCB Ground Plane 23b. FSPCB Power Plane 23d. FSPCB Bottom Layer Figure 23. FSPCB Evaluation Board 4-Layer PCB Layout Patterns AD9851/FSPCB Evaluation Board Parts List—GSO 0516(A) Miscellaneous Hardware 1 Amp 552742-1, 36-Pin Plastic, Right Angle, PC Mount, Female 1 Banana Jack–Color Not Important 1 Yellow Banana Jack 1 Black Banana Jack 2 BNC Coax.
PAGE 21
AD9851 AD9851/CGPCB CLOCK GENERATOR EVALUATION BOARD (SSOP PACKAGE) J2 +V BANANA J3 JACKS J4 5V BNC GND D3 1 D3 D5 27 D5 U1 AD9851 D1 3 D1 D6 26 D6 D0 4 D0 GND DGND +V 6 PVCC J8 BNC R6 200 R4 100k C16 4.
PAGE 22
AD9851 25a. CGPCB Top Layer 25c. CGPCB Power Plane 25b. CGPCB Ground Plane 25d. CGPCB Bottom Layer Figure 25. FSPCB Evaluation Board 4-Layer PCB Layout Patterns –22– REV.
PAGE 23
AD9851 CGPCB Evaluation Board Parts List—GSO 0515(B) Miscellaneous Hardware 1 Amp 552742-1, 36-Pin Plastic, Right Angle, PC Mount, Female 1 Banana Jack—Color Not Important 1 Yellow Banana Jack 1 Black Banana Jack 5 BNC Coax.
PAGE 24
AD9851 OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) C00633–0–1/04(D) Dimensions shown in millimeters 10.50 10.20 9.90 28 15 5.60 5.30 5.00 8.20 7.80 7.40 14 1 1.85 1.75 1.65 2.00 MAX 0.10 COPLANARITY 0.25 0.09 0.05 MIN 0.65 BSC 0.38 0.22 SEATING PLANE 8 4 0 0.95 0.75 0.55 COMPLIANT TO JEDEC STANDARDS MO-150AH Revision History Location Page 1/04—Data Sheet changed from REV. C to REV. D Renumbered figures and TPCs . . . . . . . . . . . . . . . . . . . . . . .