Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9858BSVZ

1 GSPS Direct Digital Synthesizer

AD9858

Rev. C

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FEATURES

1 GSPS internal clock speed

Up to 2 GHz input clock (selectable divide-by-2)

Integrated 10-bit DAC

Excellent phase noise and SFDR

32-bit programmable frequency register

Simplified 8-bit parallel and SPI serial control interface

Automatic frequency sweeping capability

4 frequency profiles

3.3 V power supply

Power dissipation: 2 W typical

Integrated programmable charge pump and phase

frequency detector with fast lock circuit

Isolated charge pump supply up to 5 V

Integrated 2 GHz mixer

APPLICATIONS

VHF/UHF LO synthesis

Tuners

Instrumentation

Agile clock synthesis

Cellular base station hopping synthesizers

Radars

SONET/SDH clock synthesis

GENERAL DESCRIPTION

The AD9858 is a direct digital synthesizer (DDS) featuring a

10-bit digital-to-analog converter (DAC) operating up to 1 GSPS.

The AD9858 uses advanced DDS technology coupled with an

internal high speed, high performance DAC to form a digitally

programmable, complete high frequency synthesizer capable of

generating a frequency-agile analog output sine wave at up to

400 MHz. The AD9858 is designed to provide fast frequency

hopping and fine tuning resolution (32-bit frequency tuning

word). The frequency tuning and control words are loaded into

the AD9858 via parallel (8-bit) or serial loading formats. The

AD9858 contains an integrated charge pump (CP) and phase

frequency detector (PFD) for synthesis applications requiring

the combination of a high speed DDS along with phase-locked

loop (PLL) functions. An analog mixer is also provided on chip

for applications requiring the combination of a DDS, PLL, and

mixer, such as frequency translation loops and tuners. The AD9858

also features a divide-by-2 on the clock input, allowing the external

reference clock to be as high as 2 GHz.

The AD9858 is specified to operate over the extended industrial

temperature range of –40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

03166-001

ANALOG

MULTIPLIER

PHASE ACCUMULATOR

DIV

LO IF RF

CPISET

RESET

DACISET

IOUT

FUD

SYNCLK

REFCLK

I/O PORT

(SER/PAR)

DIGITAL PLL

DELTA

FREQUENCY

WORD

DELTA

FREQUENCY

RAMP RATE

FREQUENCY

ACCUMULATOR

RESET

FREQUENCY

TUNING

WORD

PHASE

ACCUMULATOR

RESET

SYNC

PHASE

OFFSET

ADJUST

DAC

SYSCLK

CHARGE

PUMP

POWER-

DOWN

LOGIC

PS0 PS1

PHASE

DETECTOR

TIMING AND CONTROL LOGIC

PHASE-TO-

AMPLITUDE

CONVERSION

÷ M

÷ 8

÷ 2

CONTROL REGISTERS

÷ N

AD9858

FREQUENCY ACCUMULATOR

15 10

RFIFLO

Figure 1.

Summary of content (32 pages)

PAGE 1
GSPS Direct Digital Synthesizer AD9858 FEATURES GENERAL DESCRIPTION 1 GSPS internal clock speed Up to 2 GHz input clock (selectable divide-by-2) Integrated 10-bit DAC Excellent phase noise and SFDR 32-bit programmable frequency register Simplified 8-bit parallel and SPI serial control interface Automatic frequency sweeping capability 4 frequency profiles 3.
PAGE 2
AD9858 TABLE OF CONTENTS Features .............................................................................................. 1 Component Blocks ..................................................................... 14 Applications ....................................................................................... 1 Modes of Operation ................................................................... 16 General Description .........................................................................
PAGE 3
AD9858 ELECTRICAL SPECIFICATIONS Unless otherwise noted, VDD = 3.3 V ± 5%, CPVDD = 5 V ± 5%, RSET = 2 kΩ, CPISET = 2.4 kΩ, reference clock frequency = 1 GHz. Table 1.
PAGE 4
AD9858 Parameter OUTPUT PHASE NOISE CHARACTERISTICS (AT 100 MHz IOUT With 700 MHz REFCLK) At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset At 10 MHz Offset PHASE DETECTOR AND CHARGE PUMP Phase Detector Frequency Phase Detector Frequency (Divide-by-4 Enabled) 3 Charge Pump Sink and Source Current 4 Fast Lock Current (Acquisition Only) Open-Loop Current (Acquisition Only) Sink and Source Current Absolute Accuracy 5 Sink and Source Current Matching5 Input Sensitivity PDIN and
PAGE 5
AD9858 Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width Low (tPWL) Minimum Clock Pulse Width High (tPWH) Maximum Clock Rise/Fall Time Minimum Data Setup Time (tDS) Minimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) Parallel Control Bus 10 WR Minimum Low Time (tWRLOW) WR Minimum High Time (tWRHIGH) WR Minimum Period (tWR) Address to WR Setup (tASU) Address to WR Hold (tAHU) Data to WR Setup (tDSU) Data to WR Hold (tDHU) Miscellaneous Timing Specification
PAGE 6
AD9858 ABSOLUTE MAXIMUM RATINGS The AD9858 is specified for a case temperature (TCASE). To ensure that TCASE is not exceeded, an airflow source may be used. Table 2. Parameter Maximum Junction Temperature AVDD DVDD CPVDD Digital Input Voltage Range Digital Output Current Storage Temperature Range Operating Temperature Range Rating 150°C 4V 4V 6V −0.
PAGE 7
AD9858 FUD PS1 PS0 DGND DGND DVDD DVDD RESET SPSELECT AVDD AVDD AGND AGND AVDD AGND IOUT IOUT IOUT IOUT AGND DACISET DACBP AVDD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 D7 1 75 NC D6 2 74 AGND D5 3 73 AVDD D4 4 72 DIV DGND 5 71 DIV DGND 6 70 AVDD DVDD 7 69 AGND DVDD 8 68 CPGND D3 9 67 CPVDD D2 10 66 CP D1 11 65 CP 64 CPFL 63 CPGND 62 CPVDD AD9858 D0 12 TOP VIEW (Not to Sc
PAGE 8
AD9858 Pin No. 17 Mnemonic SDO I/O O 18 SDIO I/O 19 WR/SCLK I 22 RD/CS I 29, 30, 37 to 39, 41, 42, 49, 50, 52, 69, 74, 80, 85, 87, 88 31, 32, 35, 36, 40, 43, 44, 47, 48, 51, 70, 73, 77, 86, 89, 90 33 AGND I Description This is valid for serial programming mode only. When operating the I/O port as a 3-wire serial port, this pin serves as a unidirectional serial data output pin. When operated as a 2-wire serial port, this pin is unused. This is valid for serial programming mode only.
PAGE 9
AD9858 TYPICAL PERFORMANCE CHARACTERISTICS 0 MARKER 1 [T1] –0.59dBm 26.0MHz REF LVL 5dBm 1 RBW VBW SWT 5kHz 5kHz 64s RF ATT UNIT 20dB REF LVL 5dBm dB MARKER 1 [T1] 1.73dBm 26.10050100MHz 0 1 RBW VBW SWT 200Hz RF ATT 200Hz 64s UNIT 20dB dB A A –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 START: 0Hz 50MHz/ 03166-103 –100 1AP 03166-A-006 –10 STOP: 500MHz –100 0 MARKER 1 [T1] –0.57dBm 65.
PAGE 10
AD9858 RBW VBW SWT 0 5kHz 5kHz 50s RF ATT 1 UNIT 20dB REF LVL 5dBm dB MARKER 1 [T1] –1.35dBm 375.10501002MHz 0 RBW VBW SWT 500Hz RF ATT 500Hz 100s UNIT 20dB dB 1 A A –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 50MHz/ STOP: 500MHz –100 RBW VBW SWT 300Hz RF ATT 300Hz 56s UNIT 500kHz/ SPAN 5MHz Figure 12. Narrow-Band SFDR, 375 MHz fOUT, 1 MHz BW Figure 9. Wideband SFDR, 375 MHz fOUT REF LVL 5dBm CENTER 375.
PAGE 11
–50 –60 –70 –80 –90 –100 –110 –120 –130 –140 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M PHASE NOISE, L(f) (dBc/Hz) –100 –110 –120 –130 –140 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M 03166-016 –150 –160 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 Figure 16. Fractional Divider Loop Residual Phase Noise, fIN = 115 MHz, fOUT = 1550 MHz, Loop BW = 50 kHz DELTA 1 [T1] REF LVL 0dBm 0.0dB 0.00000000Hz RBW VBW SWT 1kHz 1kHz 3.
PAGE 12
AD9858 RBW VBW SWT 0.0dB 0.00000000Hz 5kHz 5kHz 15s RF ATT 10dB UNIT REF LVL 0dBm dBm 0 0 ∗ A –10 –10 –20 –20 –30 –50 –50 –60 –60 –70 –70 –80 –80 03166-017 –40 –90 CENTER 1.55GHz 15MHz/ DELTA 1 [T1] –81.10dB 57.11422845kHz 0 1 RBW VBW SWT SPAN 150MHz 1kHz 500kHz 7.6s RF ATT RF ATT 10dB UNIT dBm 1 A 1AP 1 CENTER 1.55GHz 15MHz/ SPAN 150MHz Figure 24. Fractional Divider Loop SFDR, fIN = 97.
PAGE 13
AD9858 600 2.0 3.3V 1.8 SUPPLY CURRENT (mA) 1.4 1.2 1.0 0.8 0.6 0.4 0 225 450 675 REFCLK (MHz) 900 300 200 100 03166-A-025 0.2 3.1V 400 0 1125 0 70 140 210 280 350 fOUT (MHz) Figure 27. Power Dissipation vs. REFCLK (Single-Tone Mode, fOUT = REFCLK/5) Rev. C | Page 13 of 32 Figure 28. Supply Current vs. fOUT (1 GHz REFCLK) 420 03166-024 POWER DISSIPATION (W) 1.6 0 3.
PAGE 14
AD9858 THEORY OF OPERATION The AD9858 DDS is a flexible device that can address a wide range of applications. The device consists of a numerically controlled oscillator (NCO) with a 32-bit phase accumulator, 14-bit phase offset adjustment, a power efficient DDS core, and a 1 GSPS, 10-bit DAC. The AD9858 incorporates additional capabilities for automated frequency sweeping. The device also offers an analog mixer, a PFD, and a programmable CP with advanced fast lock capability.
PAGE 15
AD9858 The charge pump output reference current is determined by an external resistor (~2.4 kΩ), which establishes a 500 μA maximum internal baseline current (ICP0). The baseline current is scaled to provide the appropriate drive current for the various operating modes (frequency detect, wide closed-loop, and final closedloop) of the CP.
PAGE 16
AD9858 When frequency detection occurs, the loop is closed and the loop is locked based on the current programmed for the wide closed-loop mode. It is important that the loop be designed for closed-loop stability while in the wide closed-loop mode. In this mode, less phase margin can usually be tolerated, because this mode is only used to enhance the lock time but is not used in the locked free running state.
PAGE 17
AD9858 Single-Tone Mode When the decimal number is calculated, it must be rounded to an integer and converted to a 32-bit binary value. The frequency resolution of the AD9858 is 0.233 Hz when the SYSCLK is 1 GHz. When in single-tone mode, the AD9858 generates a signal, or tone, of a single desired frequency. This frequency is set by the value loaded by the user into the chip’s FTW register. This frequency can be between 0 Hz and somewhat below one-half of the DAC sampling frequency (SYSCLK).
PAGE 18
AD9858 Full Sleep Mode A DFRRW value of 0 written to the register stops all frequency sweeping. There is no automated stop-at-a-given-frequency function. The user must calculate the time interval required to reach the final frequency and then issue a command to write 0 into the DFRRW register. The time required for a frequency sweep is calculated by SYSCLK 2 SYNCHRONIZATION DFRRW × DFTW SYNCLK and FUD Pins Timing for the AD9858 is provided via the user-supplied REFCLK input.
PAGE 19
AD9858 SYSCLK FUD REGISTERED FUD REGISTERED FUD EDGE DETECTED FUD EDGE DETECTED SYNCLK FUD* CONTROL REGISTER DATA VALUE 2 VALUE 1 (ASYNCHRONOUSLY LOADED VIA I/O PORT) VALUE 0 (ASYNCHRONOUSLY LOADED VIA I/O PORT) VALUE 1 VALUE 2 * FUD IS AN INPUT PROVIDED BY THE USER THAT MUST BE SET UP AND HELD AROUND RISING EDGES OF SYNCLK. THE OCCURRENCE OF THE RISING EDGE OF SYNCLK DURING THE HIGH STATE OF THE UPDATE REGS SIGNAL CAUSES THE BUFFER MEMORY CONTENTS TO BE TRANSFERRED INTO THE CONTROL REGISTERS.
PAGE 20
AD9858 I/O Port Functionality Parallel Programming Mode The I/O port can operate in either serial or parallel programming mode. Mode selection is accomplished via the SPSELECT pin. In parallel programming mode, the I/O port makes use of eight bidirectional data pins (D7 to D0), six address input pins (ADDR5 to ADDR0), a read input pin (RD), and a write input pin (WR). A register is selected by providing the proper address combination as defined in the register map (see Table 6).
PAGE 21
AD9858 ADDR[5:0] A1 A2 D[7:0] D1 D2 A3 D3 RD tRDLOV tRDHOZ tADV SPECIFICATION tADV tAHD tRDLOV tRDHOZ VALUE DESCRIPTION 15ns 5ns 15ns 10ns ADDRESS TO DATA VALID TIME (MAXIMUM) ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM) RD LOW TO OUTPUT VALID (MAXIMUM) RD HIGH TO DATA THREE-STATE (MAXIMUM) 03166-039 tAHD Figure 36.
PAGE 22
AD9858 REGISTER MAP The registers are listed in Table 6. The serial address and parallel address numbers associated with each of the registers are shown in hexadecimal format. Square brackets [] are used to reference specific bits or ranges of bits. For example, [3] designates Bit 3, and [7:3] designates the range of bits from 7 down to 3, inclusive. Table 6. Register Name Control function register (CFR) Address Ser Par 0x00 0x00 [7:0] 0x01 [15:8] 0x02 [23:16] 0x03 [31:24] Delta freq.
PAGE 23
AD9858 Register Name Phase Offset Word 2 (POW2) Frequency Tuning Word 3 (FTW3) Address Ser Par 0x08 0x1A 0x1B Phase Offset Word 3 (POW3) Reserved 0x0A 0x09 0x0B (MSB) Bit 7 0x1C 0x1D 0x1E 0x1F 0x20 0x21 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Phase Offset Word 2[7:0] Phase Offset Word 2[13:8] Not used Reserved, do not write, leave at 0xFF Reserved, do not write, leave at 0xFF REGISTER BIT DESCRIPTIONS The CFR comprises four bytes.
PAGE 24
AD9858 CFR[22]: Auto Clear Phase Accumulator Bit CFR[13]: Charge Pump Offset Bit When CFR[22] = 0 (default), a new frequency tuning word is applied to the input of the phase accumulator and added to the currently stored value. When CFR[13] = 0 (default), the charge pump operates with normal current settings. When CFR[22] = 1, this bit automatically synchronously clears (loads zeros into) the phase accumulator for one cycle upon reception of the FUD sequence indicator.
PAGE 25
AD9858 CFR[4:2]: Power-Down Bits Active high (Logic 1) powers down the respective function. Writing a Logic 1 to all three bits causes the device to enter full sleep mode. CFR[4] is used to shut down the analog mixer stage (default = 1). CFR[3] is used to shut down the phase detector and charge pump circuitry (default = 1). CFR[2] is used to shut down the DDS core and DAC and to stop all internal clocks except SYNCLK (default = 0).
PAGE 26
AD9858 Profile Selection A profile consists of a specific group of memory registers (see Table 6). In the AD9858, each profile contains a 32-bit frequency tuning word and a 14-bit phase offset word. Each profile is selectable via two external profile select pins (PS0 and PS1), as defined in Table 12. The specific mapping of registers to profiles is detailed in the Register Bit Descriptions section.
PAGE 27
AD9858 APPLICATIONS INFORMATION FREQUENCY TUNING WORD 32 fREF DC TO 400MHz 10 DDS 1GSPS DAC DC TO 150MHz PHASE/ FREQUENCY DETECTOR 150MHz DIVIDER 1/2/4 FILTER VCO CHARGE PUMP 0.5mA TO 2mA (0.5mA STEPS) DDS/DAC CLOCK 1000MHz LOOP FILTER 2GHz ±150MHz ANALOG MIXER DIVIDER 1/2 AD9858 2GHz FILTER 2GHz 03166-040 FIXED LOOP (LO1) Figure 37.
PAGE 28
AD9858 EVALUATION BOARDS The AD9858 has three different evaluation board designs. The first design is the traditional DDS evaluation board (see Figure 38). In this design, the DDS is clocked and the output is taken directly from the DAC. The analog mixer and PLL blocks are made available for separate evaluation. The second design is a fractional divide loop (see Figure 39). This evaluation board was designed to incorporate the DDS, the phase frequency detector, and the charge pump.
PAGE 29
AD9858 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 1 SEATING PLANE 76 76 75 100 1 75 PIN 1 BOTTOM VIEW (PINS UP) TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 51 50 25 50 1.05 1.00 0.95 7° 3.5° 0° 0.27 0.22 0.17 0.50 BSC 0.15 0.05 26 6.50 NOM COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD 021809-A 51 25 26 0.20 0.
PAGE 30
AD9858 NOTES Rev.
PAGE 31
AD9858 NOTES Rev.