Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9859YSVZ

400 MSPS, 10-Bit, 1.8 V CMOS

Direct Digital Synthesizer

AD9859

Rev. A

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FEATURES

400 MSPS internal clock speed

Integrated 10-bit DAC

32-bit tuning word

Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)

Excellent dynamic performance

>75 dB SFDR @ 160 MHz (±100 kHz offset) A

OUT

Serial I/O control

1.8 V power supply

Software and hardware controlled power-down

48-lead TQFP/EP package

Support for 5 V input levels on most digital inputs

PLL REFCLK multiplier (4× to 20×)

Internal oscillator; can be driven by a single crystal

Phase modulation capability

Multichip synchronization

APPLICATIONS

Agile LO frequency synthesis

Programmable clock generators

Test and measurement equipment

Commercial and amateur radio exciter

GENERAL DESCRIPTION

The AD9859 is a direct digital synthesizer (DDS) featuring a

10-bit DAC operating at up to 400 MSPS. The AD9859 uses

advanced DDS technology, coupled with an internal high speed,

high performance DAC to form a digitally programmable,

complete high frequency synthesizer capable of generating a

frequency-agile analog output sinusoidal waveform at up to

200 MHz. The AD9859 is designed to provide fast frequency

hopping and fine tuning resolution (32-bit frequency tuning

word). The frequency tuning and control words are loaded into

the AD9859 via a serial I/O port.

The AD9859 is specified to operate over the extended industrial

temperature range of –40°C to +105°C

FUNCTIONAL BLOCK DIAGRAM

COS(X)

CONTROL REGISTERS

OSCILLATOR/BUFFER

SYNC

ENABLE

I/O UPDATE

DAC_R

SET

DDS CORE

PHASE

OFFSET

PHASE

ACCUMULATOR

–1

IOUT

OSK

PWRDWNCTL

REFCLK

CRYSTAL OUT I/O PORT

DDS CLOCK

FREQUENCY

TUNING WORD

AMPLITUDE

SCALE FACTOR

PHASE

ACUMULATOR

RESET

DAC

SYSTEM

CLOCK

SYSTEM

CLOCK

SYNC_IN

SYNC_CLK

RESET

TIMING AND CONTROL LOGIC

4–20

CLOCK

MULTIPLIER

÷ 4

AD9859

1932 10

03375-0-001

Figure 1.

Summary of content (24 pages)

PAGE 1
400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer AD9859 FEATURES APPLICATIONS 400 MSPS internal clock speed Integrated 10-bit DAC 32-bit tuning word Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output) Excellent dynamic performance >75 dB SFDR @ 160 MHz (±100 kHz offset) AOUT Serial I/O control 1.
PAGE 2
AD9859 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 11 Applications ....................................................................................... 1 Component Blocks ..................................................................... 11 General Description ......................................................................
PAGE 3
AD9859 AD9859—ELECTRICAL SPECIFICATIONS Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, RSET = 3.92 kΩ, External Reference Clock Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND. Table 1.
PAGE 4
AD9859 Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width Low Minimum Clock Pulse Width High Maximum Clock Rise/Fall Time Minimum Data Setup Time DVDD_I/O = 3.3 V Minimum Data Setup Time DVDD_I/O = 1.8 V Minimum Data Hold Time Maximum Data Valid Time Wake-Up Time2 Minimum Reset Pulse Width High I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.
PAGE 5
AD9859 ABSOLUTE MAXIMUM RATINGS Table 2. Rating 150°C 4V 2V –0.7 V to +5.25 V –0.7 V to +2.2 V 5 mA –65°C to +150°C –40°C to +105°C 300°C 38°C/W 15°C/W DIGITAL INPUTS ESD CAUTION DAC OUTPUTS DVDD_I/O IOUT IOUT INPUT AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS. MUST TERMINATE OUTPUTS TO AVDD. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. Figure 2. Equivalent Input and Output Circuits Rev.
PAGE 6
AD9859 DGND DGND OSK SYNC_CLK SYNC_IN DVDD_I/O DGND SDIO SCLK CS SDO IOSYNC PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 1 36 RESET DVDD 2 35 PWRDWNCTL DGND 3 34 DVDD AVDD 4 33 DGND AGND 5 32 AGND AVDD 6 31 AGND AGND 7 30 AGND OSC/REFCLK 8 29 AVDD OSC/REFCLK 9 28 AGND CRYSTAL OUT 10 27 AVDD CLKMODESELECT 11 26 AGND LOOP_FILTER 12 25 AVDD AD9859 16 17 18 19 20 21 22 23 24 AVDD AVDD AVDD IOUT IOUT AGND DACBP DAC_RSE
PAGE 7
AD9859 PIN FUNCTION DESCRIPTIONS Table 3. Pin Function Descriptions—48-Lead TQFP/EP Pin No. 1 Mnemonic I/O UPDATE I/O I 2, 34 3, 33, 42, 47, 48 4, 6, 13, 16, 18, 19, 25, 27, 29 5, 7, 14, 15, 17, 22, 26, 28, 30, 31, 32 8 DVDD DGND I I Description The rising edge transfers the contents of the internal buffer memory to the I/O registers. This pin must be set up and held around the SYNC_CLK output signal. Digital Power Supply Pins (1.8 V). Digital Power Ground Pins. AVDD I Analog Power Supply Pins (1.
PAGE 8
AD9859 TYPICAL PERFORMANCE CHARACTERISTICS REF LVL –5dBm RF ATT 20dB UNIT REF LVL –5dBm dB RBW 10kHz VBW 10kHz SWT 5s RF ATT 20dB UNIT dB 0 1 1 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 1 –70 1 –70 –80 03375-0-003 –80 –90 –100 CENTER 100MHz 20MHz/ –90 –100 CENTER 100MHz SPAN 200MHz Figure 4. FOUT = 1 MHz FCLK = 400 MSPS, WBSFDR REF LVL –5dBm 0 DELTA [T1] –60.96dB 79.75951904MHz DELTA [T1] –65.02dB 81.
PAGE 9
AD9859 RBW VBW SWT DELTA [T1] –81.87dB 96.19238477kHz RF ATT 20dB UNIT dB 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 03375-0-009 –90 –100 CENTER 1.16MHz 200kHz/ DELTA [T1] –89.33dB –801.60320641kHz 0 RBW VBW SWT CENTER 79.76MHz REF LVL –8dBm dB –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 03375-0-010 –10 –20 1 –100 200kHz/ DELTA [T1] –84.92dB 997.
PAGE 10
AD9859 Figure 16. Residual Phase Noise with FOUT = 159.5 MHz, FCLK = 400 MSPS (Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue) Figure 17. Residual Phase Noise with FOUT = 9.5 MHz, FCLK = 400 MSPS (Green), 4 ×100 MSPS (Red), and 20 × 20 MSPS (Blue) Rev.
PAGE 11
AD9859 THEORY OF OPERATION COMPONENT BLOCKS DDS Core Clock Input The output frequency (fO) of the DDS is a function of the frequency of the system clock (SYSCLK), the value of the frequency tuning word (FTW), and the capacity of the accumulator (232 in this case). The exact relationship is given below with fS defined as the frequency of SYSCLK. The AD9859 supports various clock methodologies.
PAGE 12
AD9859 DAC Output Serial I/O Port The AD9859 incorporates an integrated 10-bit current output DAC. Unlike most DACs, this output is referenced to AVDD, not AGND. The AD9859 serial port is a flexible, synchronous serial communications port that allows easy interface to many industrystandard microcontrollers and microprocessors. The serial I/O port is compatible with most synchronous transfer formats, including both the Motorola 6905/11 SPI® and Intel® 8051 SSR protocols.
PAGE 13
AD9859 Table 5. Register Map Register Name (Serial Address) Control Function Register No.1 (CFR1) (0x00) Bit Range (MSB) Bit 7 Bit 6 Bit 5 Bit 4 <7:0> Digital PowerDown Not Used DAC PowerDown Clock Input PowerDown <15:8> Not Used Not Used AutoClr Phase Accum Enable SINE Output <23:16> Automatic Sync Enable Software Manual Sync Control Function Register No.
PAGE 14
AD9859 Control Register Bit Descriptions Control Function Register No. 1 (CFR1) CFR1<31:27>: Not Used CFR1<22> = 1. The software controlled manual synchronization feature is executed. The SYNC_CLK rising edge is advanced by one SYNC_CLK cycle and this bit is cleared. To advance the rising edge multiple times, this bit needs to be set for each advance. See the Synchronizing Multiple AD9859s section for details. CFR1<26>: Amplitude Ramp Rate Load Control Bit CFR1<21:14>: Not Used CFR1<26> = 0 (default).
PAGE 15
AD9859 CFR1<6>: Not Used CFR1<5>: DAC Power-Down Bit CFR1<5> = 0 (default). The DAC is enabled for operation. CFR1<5> = 1. The DAC is disabled and is in its lowest power dissipation state. CFR1<4>: Clock Input Power-Down Bit CFR2<11> = 1. The high speed sync enhancement is on. This bit should be set when attempting to use the auto-synchronization feature for SYNC_CLK inputs beyond 50 MHz, (200 MSPS SYSCLK). See the Synchronizing Multiple AD9859s section for details.
PAGE 16
AD9859 Other Register Descriptions Amplitude Scale Factor (ASF) The ASF register stores the 2-bit auto ramp rate speed value and the 10-bit amplitude scale factor used in the output shaped keying (OSK) operation. In auto OSK operation, ASF <15:14> tells the OSK block how many amplitude steps to take for each increment or decrement. ASF<13:0> sets the maximum value achievable by the OSK internal multiplier. In manual OSK mode, ASF<15:14> has no effect. ASF <13:0> provide the output scale factor directly.
PAGE 17
AD9859 AUTO Shaped On-Off Keying Mode Operation OSK Ramp Rate Timer The auto-shaped on-off keying mode is active when CFR1<25> and CFR1<24> are set. When auto-shaped on-off keying mode is enabled, a single scale factor is internally generated and applied to the multiplier input for scaling the output of the DDS core block (see Figure 18). The scale factor is the output of a 10-bit counter that increments/decrements at a rate determined by the contents of the 8-bit output ramp rate register.
PAGE 18
AD9859 External Shaped On-Off Keying Mode Operation contents into the control registers of the device. The combination of the SYNC_CLK and I/O UPDATE pins provides the user with constant latency relative to SYSCLK, and also ensures phase continuity of the analog output signal when a new tuning word or phase offset value is asserted. Figure 19 demonstrates an I/O UPDATE timing cycle and synchronization.
PAGE 19
AD9859 SYSCLK A B A B SYNC_CLK I/O UPDATE DATA IN REGISTERS DATA 1 DATA 2 DATA 3 DATA 0 DATA 1 THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B. DATA 2 03375-007 DATA IN I/O BUFFERS Figure 20. I/O Synchronization Timing Diagram Synchronizing Multiple AD9859s The AD9859 allows easy synchronization of multiple AD9859s.
PAGE 20
AD9859 during Phase 2 of the communication cycle is a function of the register being accessed. For example, when accessing the Control Function Register 2, which is three bytes wide, Phase 2 requires that three bytes be transferred. If accessing the frequency tuning word, which is four bytes wide, Phase 2 requires that four bytes be transferred. After transferring all data bytes per the instruction, the communication cycle is completed. There are two phases to a communication cycle with the AD9859.
PAGE 21
AD9859 INSTRUCTION BYTE The instruction byte contains the following information: Table 7. MSB R/W D6 X D5 X D4 A4 D3 A3 R/W—Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. Logic High indicates read operation. Logic 0 indicates a write operation. X, X—Bits 6 and 5 of the instruction byte are Don’t Cares.
PAGE 22
AD9859 When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is high, the AD9859 is put into a fast recovery power-down mode. In this mode, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry is NOT powered down. Table 8 indicates the logic level for each power-down bit that drives out of the AD9859 core logic to the analog section and the digital clock generation section of the chip for the external power-down operation.
PAGE 23
AD9859 SUGGESTED APPLICATION CIRCUITS 03375-0-015 LPF AD9859 FREQUENCY TUNING WORD MODULATED/ DEMODULATED SIGNAL RF/IF INPUT REFCLK PHASE OFFSET WORD 1 I/I BASEBAND REFCLK CRYSTAL Figure 25. Synchronized LO for Upconversion/Down Conversion AD9859 DDS IOUT IOUT LPF REFCLK CRYSTAL OUT SYNC OUT RF OUT SYNC IN AD9859 DDS LOOP FILTER VCO FILTER IOUT LPF REFCLK AD9859 TUNING WORLD IOUT FREQUENCY TUNING WORD PHASE OFFSET WORD 2 Q/Q BASEBAND Figure 27.
PAGE 24
AD9859 OUTLINE DIMENSIONS 9.00 BSC SQ 1.20 MAX BOTTOM VIEW (PINS UP) 37 36 48 1 37 36 48 1 7.00 BSC SQ PIN 1 3.50 SQ TOP VIEW (PINS DOWN) 0° MIN 1.05 1.00 0.95 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY EXPOSED PAD 12 13 VIEW A 25 24 25 24 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 12 13 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.