Datasheet

AD9859
Rev. A | Page 13 of 24
Table 5. Register Map
Register
Name
(Serial
Address)
Bit
Range
(MSB)
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
Control
Function
Register
No.1
(CFR1)
(0x00)
<7:0>
Digital
Power-
Down
Not Used
DAC
Power-
Down
Clock Input
Power-
Down
External
Power-
Down
Mode
Not Used
SYNC_CLK
Out
Disable
Not
Used
0x00
<15:8> Not Used Not Used
AutoClr
Phase
Accum
Enable SINE
Output
Not Used
Clear
Phase
Accum.
SDIO
Input
Only
LSB First
0x00
<23:16>
Automatic
Sync
Enable
Software
Manual
Sync
Not Used
0x00
<31:24> Not Used
Load ARR
@ I/O UD
OSK
Enable
Auto
OSK
Keying
0x00
Control
Function
Register No.
2 (CFR2)
(0x01)
<7:0>
REFCLK Multiplier
0x00 or 0x01, or 0x02 or 0x03: Bypass Multiplier
0x04 to 0x14: 4× to 20× Multiplication
VCO
Range
Charge Pump Current
<1:0>
0x00
<15:8> Not Used
High
Speed
Sync
Enable
Hardware
Manual
Sync
Enable
CRYSTAL
OUT Pin
Active
Not
Used
0x00
<23:16> Not Used 0x18
Amplitude
Scale Factor
(ASF)
(0x02)
<7:0> Amplitude Scale Factor Register <7:0> 0x00
<15:8>
Auto Ramp Rate Speed
Control <1:0>
Amplitude Scale Factor Register <13:8>
0x00
Amplitude
Ramp Rate
(ARR)
(0x03)
<7:0> Amplitude Ramp Rate Register <7:0>
0x00
Frequency
Tuning
Word
(FTW0)
(0x04)
<7:0> Frequency Tuning Word No. 0 <7:0> 0x00
<15:8> Frequency Tuning Word No. 0 <15:8> 0x00
<23:16> Frequency Tuning Word No. 0 <23:16> 0x00
<31:24> Frequency Tuning Word No. 0 <31:24>
0x00
Phase
Offset Word
(POW0)
(0x05)
<7:0> Phase Offset Word No. 0 <7:0> 0x00
<15:8> Not Used<1:0> Phase Offset Word No. 0 <13:8>
0x00