Datasheet

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High Performance

HDMI/DVI Transmitter

AD9889B

Rev. A

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FEATURES

General

HDMI

™

/DVI transmitter compatible with HDMI v. 1.3,

DVI v. 1.0, and HDCP v. 1.2

Single 1.8 V power supply

Video/audio inputs accept logic levels from 1.8 V to 3.3 V

80-lead LQFP, Pb-free package

64-lead LFCSP, Pb-free package

76-ball CSP_BGA, Pb-free package

Digital video

165 MHz operation supports all resolutions from 480i to

1080p and UXGA at 60 Hz

Programmable two-way color space converter

Supports RGB, YCbCr, and DDR

Supports ITU656-based embedded syncs

Automatic input video format timing detection (CEA-861B)

Digital audio

Supports standard S/PDIF for stereo LPCM or compressed

audio up to 192 kHz

8-channel, uncompressed, LPCM I

S audio up to 192 kHz

Special features for easy system design

On-chip MPU with I

C® master to perform HDCP

operations and EDID reading operations

5 V tolerant I

C and HPD I/Os, no extra device needed

No audio master clock needed for supporting S/PDIF

and I

On-chip MPU reports HDMI events through interrupts and

registers

APPLICATIONS

DVD players and recorders

Digital set-top boxes

A/V receivers

Digital cameras and camcorders

HDMI repeater/splitter

GENERAL DESCRIPTION

The AD9889B is a 165 MHz, high definition multimedia inter-

face (HDMI) v. 1.3 transmitter. It supports HDTV formats up to

1080p, and computer graphic resolutions up to UXGA (1600 ×

1200 @ 60 Hz). With the inclusion of HDCP, the AD9889B allows

the secure transmission of protected content as specified by the

HDCP v. 1.2 protocol.

FUNCTIONAL BLOCK DIAGRAM

SCL

DDCSDA

DDCSCL

HPD

INTERRUPT

HANDLER

HDCP-EDID

MICRO-

CONTROLLER

HDCP

CORE

MASTER

SLAVE

CONFIGURATION

LOGIC

HDMI

CORE

XOR

MASK

COLOR

SPACE

CONVER-

SION

4:2:2 TO

4:4:4

CONVER-

SION

VIDEO

DATA

CAPTURE

AUDIO

DATA

CAPTURE

Tx0–/Tx0+

Tx1–/Tx1+

Tx2–/Tx2+

TxC–/TxC+

CLK

VSYNC

HSYNC

D[23:0]

S/PDIF

MCLK

S[3:0]

LRCLK

SCLK

MDAMCL

AD9889B

06291-001

Figure 1.

The AD9889B supports both S/PDIF and 8-channel I

S audio.

Its high fidelity, 8-channel I

S can transmit either stereo or 7.1

surround audio at 192 kHz. The S/PDIF can carry stereo LPCM

audio or compressed audio, including DTS®, THX®, and Dolby®

Digital.

The AD9889B helps reduce system design complexity and cost

by incorporating such features as an internal MPU for HDCP

operations, an I

C master for EDID reading, a single 1.8 V power

supply, and 5 V tolerance on the I

C and hot plug detect pins.

Fabricated in an advanced CMOS process, the AD9889B is

available in a space-saving, 76-ball CSP_BGA or 64-lead LFCSP

surface-mount package, and an 80-lead LQFP surface-mount

package. All packages are available as Pb-free and are specified

from −25°C to +85°C.

Summary of content (12 pages)

PAGE 1
High Performance HDMI/DVI Transmitter AD9889B FEATURES APPLICATIONS DVD players and recorders Digital set-top boxes A/V receivers Digital cameras and camcorders HDMI repeater/splitter GENERAL DESCRIPTION The AD9889B is a 165 MHz, high definition multimedia interface (HDMI) v. 1.3 transmitter. It supports HDTV formats up to 1080p, and computer graphic resolutions up to UXGA (1600 × 1200 @ 60 Hz).
PAGE 2
AD9889B TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .................................................................9 Applications ....................................................................................... 1 Design Resources ..........................................................................9 General Description ....................................................................
PAGE 3
AD9889B SPECIFICATIONS Table 1.
PAGE 4
AD9889B Parameter AUDIO AC TIMING Sample Rate I2S Cycle Time I2S Setup Time I2S Hold Time Audio Pipeline Delay 1 2 Conditions Temp Test Level 1 I2S and S/PDIF Full 25°C 25°C 25°C 25°C IV IV IV IV IV See Explanation of Test Levels section. UI = unit interval. Rev.
PAGE 5
AD9889B ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS Table 2. Parameter Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating +5.5 V to −0.3 V 20 mA −40°C to +85°C −65°C to +150°C 150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 6
AD9889B DVDD DVDD DVDD DVDD D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 GND GND PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 GND 59 GND 3 58 D15 HSYNC 4 57 D16 VSYNC 5 56 D17 CLK 6 55 D18 S/PDIF 7 54 D19 MCLK 8 53 D20 AD9889B 52 D21 TOP VIEW (Not to Scale) 51 D22 50 D23 I2S3 12 49 MCL SCLK 13 48 MDA LRCLK 14 47 SDA GND 15 46 SCL PVDD 16 45 DDCSDA GND 17 44 DDCSCL GND 18
PAGE 7
AD9889B 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J 06291-004 K BOTTOM VIEW (Not to Scale) Figure 4. 76-Ball BGA Configuration (Top View) Table 3. Pin Function Descriptions Pin No. LFCSP 39 to 47, 50 to 63, 2 LQFP 50 to 58, 65 to 78, 2 Mnemonic D[23:0] Type 1 I Description Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V.
PAGE 8
AD9889B BGA K7, K8 Pin No.
PAGE 9
AD9889B APPLICATIONS INFORMATION DESIGN RESOURCES DOCUMENT CONVENTIONS Analog Devices, Inc. evaluation kits, reference design schematics, and other support documentation are available under the nondisclosure agreement (NDA) from ATV_VideoTx_Apps@analog.com. In this data sheet, data is represented using the conventions described in Table 4. Table 4. Document Conventions Other resources include: EIA/CEA-861B, which describes audio and video infoframes as well as the E-EDID structure for HDMI.
PAGE 10
AD9889B PCB LAYOUT RECOMMENDATIONS The AD9889B is a high precision, high speed analog device. As such, to obtain the maximum performance from the part, it is important to have a well laid out board. Other Input Signals POWER SUPPLY BYPASSING The PD/A0 input pin can be connected to GND or supply (through a resistor or a control signal). The device address and power-down polarity are set by the state of the PD/A0 pin when the AD9889B supplies are applied/enabled.
PAGE 11
AD9889B OUTLINE DIMENSIONS 0.75 0.60 0.45 16.20 16.00 SQ 15.80 1.60 MAX 61 80 60 1 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.10 COPLANARITY 20 41 40 21 VIEW A VIEW A 0.65 BSC LEAD PITCH 0.38 0.32 0.22 051706-A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BEC Figure 5. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters 9.00 BSC SQ 0.60 MAX 8.75 BSC SQ 33 32 16 17 7.
PAGE 12
AD9889B A1 CORNER INDEX AREA 6.10 6.00 SQ 5.90 10 9 8 7 6 5 4 3 2 1 A B BALL A1 PAD CORNER TOP VIEW C 4.50 BSC SQ D E 0.50 BSC F G H J K BOTTOM VIEW 0.75 REF DETAIL A *1.40 MAX DETAIL A 0.65 MIN 0.15 MIN COPLANARITY 0.08 MAX *COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION TO PACKAGE HEIGHT. 010807-A 0.35 SEATING 0.30 PLANE 0.25 BALL DIAMETER Figure 7. 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 6 mm × 6 mm × 1.