Datasheet

AD9911
Rev. 0 | Page 17 of 44
APPLICATION CIRCUITS
LOOP
FILTER
PHASE
COMPARATOR
VCO
AD9911
REF CLK
REFERENCE
CHARGE
PUMP
AD9510, AD9511, ADF4106
÷
÷
05785-031
LPF
Figure 32. DDS in PLL Feedback Locking to Reference Offering Fine Frequency and Delay Adjust Tuning
AD9911
(SLAVE 1)
AD9911
(MASTER)
CLOCK
SOURCE
AD9911
(SLAVE 2)
AD9911
(SLAVE 3)
FPGA
DATA
SYNC_CLK
REF_CLK
SYNC_CLK
SYNC_CLK
FPGA
DATA
FPGA
DATA
DATA
FPGA
SYNC_CLK
C1
S1
C2
S2
C3
S3
C4
S4
A1
A2
A4
A3
A_END
CENTRAL
CONTROL
AD9510
CLOCK DISTRIBUTOR
WITH
DELAY EQUALIZATION
SYNC_OUT
AD9510
SYNCHRONIZATION
DELAY EQUALIZATION
05785-032
Figure 33. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and SYNC Clock
AD9911
REF CL
K
n
PROGRAMMABLE 1 TO 32
DIVIDER AND DELAY ADJUST
CLOCK OUTPUT
SELECTION(S)
n = DEPENDANT ON PRODUCT SELECTION.
AD9515
AD9514
AD9513
AD9512
LVPECL
LVDS
CMOS
CH 2
05785-033
LPF
Figure 34. Clock Generation Circuit Using the AD951x Series of Clock Distribution Chips