Datasheet

AD9911
Rev. 0 | Page 3 of 44
GENERAL DESCRIPTION
The DDS acts as a high resolution frequency divider with the
REF_CLK as the input and the DAC providing the output. The
REF_CLK input can be driven directly or used in combination
with an integrated REF_CLK multiplier (PLL). The REF_CLK
input also features an oscillator circuit to support an external
crystal as the REF_CLK source. The crystal can be used in
combination with the REF_CLK multiplier.
The AD9911 I/O port offers multiple configurations to provide
significant flexibility. The I/O port offers an SPI-compatible
mode of operation that is virtually identical to the SPI operation
found in earlier Analog Devices DDS products.
Flexibility is provided by four data pins (Pin SDIO_0,
Pin SDIO_1, Pin SDIO_2, and Pin SDIO_3) that allow four
programmable modes of I/O operation.
The DAC output is supply referenced and must be terminated
into AVDD by a resistor and an AVDD center-tapped trans-
former. The DAC has its own programmable reference to enable
different full-scale currents.
The DDS core (the AVDD pins and the DVDD pins) is powered
by a 1.8 V supply. The digital I/O interface (SPI) operates at
3.3 V and requires that the Pin DVDD_I/O (Pin 49) be
connected to 3.3 V.
FUNCTIONAL BLOCK DIAGRAM
AD9911
32
FTW/
ΔFTW
SYNC_CLK
CLK_MODE_SEL
BUFFER/
XTAL
OSCILLATOR
SYSTEM
CLK
1.8V
AVDD DVDD
SYNC_IN
SYNC_OUT
I/O_UPDATE
32
32
PHASE/
ΔPHASE
AMP/
ΔAMP
1014
1015
IOUT
10
DAC
IOUT
DAC_RSET
REF_CLK
REF_CLK
PWR_DWN_CTL
MASTER_RESET
SCLK
SDIO_0
SDIO_1
SDIO_2
SDIO_3
CS
TIMING AND CONTROL LOGIC
SCALABLE
DAC REF
CURRENT
MUX
MUX
I/O
PORT
BUFFER
CONTROL
REGISTERS
C
H
A
N
N
E
L
R
E
G
I
S
T
E
R
S
PROFILE
REGISTERS
÷4
REF CLOCK
MULTIPLIER
4× TO 20×
1.8V
P0 P1 P2 P3 DVDD_I/O
COS(X)
Σ
Σ
Σ Σ
DDS
CORE
DDS
CORE
DDS
CORE
SPURKILLER/
MULTI-TONE
MUX
05785-001
3.3V
LOOP FILTER
Figure 2. Functional Block Diagram