Datasheet

AD9911
Rev. 0 | Page 34 of 44
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO_1
SDIO_0
CS
D7
(D1)
D5
(D3)
D3
(D5)
D1
(D7)
D6
(D0)
D4
(D2)
D2
(D4)
D0
(D6)
I6
(I0)
I4
(I2)
I2
(I4)
I0
(I6)
I7
(I1)
I5
(I3)
I3
(I5)
I1
(I7)
05785-052
Figure 55. 2-Bit Mode Read Timing—Clock Stall High
INSTRUCTION CYCLE D
A
T
A
TRANSFER CYCLE
I7
(I3)
I1
(I5)
I5
(I1)
I3
(I7)
I6
(I2)
I0
(I4)
I4
(I0)
I2
(I6)
SCLK
SDIO_0
SDIO_1
SDIO_2
CS
SDIO_3
D7
(D3)
D1
(D5)
D5
(D1)
D3
(D7)
D6
(D2)
D0
(D4)
D4
(D0)
D2
(I6)
05785-053
Figure 56. 4-Bit Mode Read Timing—Clock Stall High