Datasheet

AD9911
Rev. 0 | Page 36 of 44
CHANNEL REGISTER MAP
Table 25.
Register Name
(Address)
Bit
Range Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
Channel
Function
1
(CFR)
(0x03)
<7:0>
Digital power-
down
DAC
power
down
Matched
pipe delays
active
Auto clear
sweep
accumulator
Clear sweep
accumulator
Auto clear
phase
accumulator
Clear phase
accumulator
2
Sine
wave
output
enable
0x02
<15:8>
Linear sweep
no-dwell
Linear
sweep
enable
Load SRR
at I/O
Update
Open Open Must be 0
DAC full-scale current
control <9:8>
0x03
<23:16>
Amplitude frequency
phase select <23:22>
Open <21:19> Data align bits for SpurKiller mode
<18:16>
0x00
<7:0> Frequency Tuning Word 0 <7:0> 0x00
<15:8> Frequency Tuning Word 0 <15:8>
<23:16> Frequency Tuning Word 0 <23:16>
Channel
Frequency Tuning
Word 0
1
(CTW0)
(0x04)
<31:24> Frequency Tuning Word 0 <31:24>
<7:0> Phase Offset Word 0 0x00
Channel Phase
1
Offset Word 0
(CPOW0) (0x05)
<15:8> Open <15:14> Phase Offset Word 0 <13:8> 0x00
<7:0> Amplitude scale factor 0x00
<15:8>
Increment/decrement
step size <15:14>
Open
Amplitude
multiplier
enable
Ramp-up/
ramp-down
enable
Load ARR at I/O
update
Amplitude scale
factor <9:8>
0x00
Amplitude
Control (ACR)
(0x06)
<23:16> Amplitude ramp rate <23:16> –
<7:0> Linear sweep rising ramp rate (RSRR) <7:0> –
Linear Sweep
Ramp Rate
1
(LSR)
(0x07)
<15:8> Linear sweep falling ramp rate (FSRR) <15:8> –
LSR Rising Delta
1
(RDW) (0x08)
<7:0> Rising delta word <7:0> –
<15:8> Rising delta word <15:8> –
<23:16> Rising delta word <23:16> –
<31:24> Rising delta word <31:24> –
LSR Falling Delta
1
(FDW) (0x09)
<7:0> Falling delta word <7:0> –
<15:8> Falling delta word <15:8> –
<23:16> Falling delta word <23:16> –
<31:24> Falling delta word <31:24> –
1
There are four sets of channel registers and profile registers, one per channel. This is not shown in the channel or profile register maps because the addresses of all
channel registers and profile registers are the same for each channel. Therefore, the channel enable bits determine if the channel registers and/or profile registers are
written to or not.
2
The clear accumulator bit is set after a master reset. It self clears when an I/O update is asserted.