Datasheet

AD9911
Rev. 0 | Page 7 of 44
Parameter Min Typ Max Unit Test Conditions/Comments
I/O PORT TIMING CHARACTERISTICS
Maximum Frequency Clock (SCLK) 200 MHz
Minimum SCLK Pulse Width Low (t
PWL
) 1.6 ns
Minimum SCLK Pulse Width High (t
PWH
) 2.2 ns
Minimum Data Set-Up Time (t
DS
) 2.2 ns
Minimum Data Hold Time 0 ns
Minimum CSB Set-Up Time (t
PRE
) 1.0 ns
Minimum Data Valid Time for Read Operation 12 ns
MISCELLANEOUS TIMING CHARACTERISTICS
Master_Reset Minimum Pulse Width 1 Minimum pulse width = 1 sync clock period
I/O_Update Minimum Pulse Width 1 Minimum pulse width = 1 sync clock period
Minimum Set-Up Time (I/O_Update to
SYNC_CLK)
4.8 ns Rising edge to rising edge
Minimum Hold Time (I/O_Update to
SYNC_CLK)
0 ns Rising edge to rising edge
Minimum Set-Up Time (Profile Inputs to
SYNC_CLK)
5.4 ns
Minimum Hold Time (Profile Inputs to
SYNC_CLK)
0 ns
Minimum Set-Up Time (SDIO Inputs to
SYNC_CLK)
2.5 ns
Minimum Hold Time (SDIO Inputs to
SYNC_CLK)
0 ns
Propagation Delay Between REF_CLK and
SYNC_CLK
2.25 3.5 5.5 ns
CMOS LOGIC INPUT
V
IH
2.0 V
V
IL
0.8 V
Logic 1 Current 3 12 μA
Logic 0 Current
−12
μA
Input Capacitance 2 pF
CMOS LOGIC OUTPUTS (1 mA Load)
V
OH
2.7 V
V
OL
0.4 V
POWER SUPPLY
Total Power Dissipation—Single-Tone Mode 241 mW Dominated by supply variation
Total Power Dissipation—With Sweep
Accumulator
241 mW Dominated by supply variation
Total Power Dissipation—3 Spur
Reduction/Multitone Channels Active
351 mW Dominated by supply variation
Total Power Dissipation—Test-Tone
Modulation
264 mW Dominated by supply variation
Total Power Dissipation—Full Power Down 1.8 mW
IAVDD—Single-Tone Mode 73 mA
IAVDD— Sweep Accumulator, REF_CLK
Multiplier, and 10-Bit Output Scalar Enabled
73 mA
IDVDD—Single-Tone Mode 50 mA
IDVDD—Sweep Accumulator, REF_CLK
Multiplier, and 10-Bit Output Scalar Enabled
50 mA
IDVDD_I/O 40 mA IDVDD = read
IDVDD_I/O 30 mA IDVDD = write
IAVDD Power-Down Mode 0.7 mA
IDVDD Power-Down Mode 1.1 mA