Inc. Recording Equipment User Manual
Table Of Contents
- Features
- Applications
- General Description
- Basic Block Diagram
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Input/Output Termination Recommendations
- Theory of Operation
- Thermal Performance
- Power-Up
- Power Supply Partitioning
- Serial Control Port
- I/O Register Map
- I/O Register Descriptions
- Serial Port Configuration (Register 0x0000 to Register 0x0005)
- Power-Down and Reset (Register 0x0010 to Register 0x0013)
- System Clock (Register 0x0020 to Register 0x0022)
- CMOS Output Divider (S-Divider) (Register 0x0100 to Register 0x0106)
- Frequency Tuning Word (Register 0x01A0 to Register 0x01AD)
- Register 0x01A0 to Register 0x01A5—Reserved
- Register 0x01A6—FTW0 (Frequency Tuning Word)
- Register 0x01A7—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01A8—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01A9—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AA—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AB—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AC—Phase
- Register 0x01AD—Phase (Continued)
- Doubler and Output Drivers (Register 0x0200 to Register 0x0201)
- Calibration (User-Accessible Trim) (Register 0x0400 to Register 0x0410)
- Harmonic Spur Reduction (Register 0x0500 to Register 0x0509)
- Outline Dimensions
AD9912
Rev. D | Page 11 of 40
06763-009
19.85 19.95 20.05 20.15 20.25 20.35
FREQUENCY (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
SIGNAL POWER (dBm)
20.1MHz
–95dBc
500kHz
300Hz
1kHz
CARRIER:
SFDR:
FREQ. SPAN:
RESOLUTION BW:
VIDEO BW:
Figure 9. Narrow-Band SFDR at 20.1 MHz,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed)
06763-010
200.85 200.95 201.05 201.15 201.25 201.35
FREQUENCY (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
SIGNAL POWER (dBm)
201.1MHz
–91dBc
500kHz
300Hz
1kHz
CARRIER:
SFDR:
FREQ. SPAN:
RESOLUTION BW:
VIDEO BW:
Figure 10. Narrow-Band SFDR at 201.1 MHz,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
06763-011
398.45 398.55 398.65 398.75 398.85 398.95
FREQUENCY (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
SIGNAL POWER (dBm)
398.7MHz
–86dBc
500kHz
300Hz
1kHz
CARRIER:
SFDR:
FREQ. SPAN:
RESOLUTION BW:
VIDEO BW:
Figure 11. Narrow-Band SFDR at 398.7 MHz,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
06763-012
100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–80
–90
–100
–110
–120
–130
–140
–150
–160
PHASE NOISE (dBc/Hz)
399MHz
99MHz
RMS JITTER (100Hz TO 40MHz):
99MHz:
399MHz:
413fs
222fs
Figure 12. Absolute Phase Noise Using HSTL Driver,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
06763-013
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–80
–90
–100
–110
–120
–130
–140
–150
–160
PHASE NOISE (dBc/Hz)
399MHz
99MHz
RMS JITTER (12kHz TO 20MHz):
99MHz:
399MHz:
0.98ps
0.99ps
Figure 13. Absolute Phase Noise Using HSTL Driver,
SYSCLK = 1 GHz (SYSCLK PLL Driven by Rohde & Schwarz SMA100 Signal
Generator at 83.33 MHz )
06763-014
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–80
–90
–100
–110
–120
–130
–140
–150
–160
PHASE NOISE (dBc/Hz)
399MHz
99MHz
RMS JITTER (12kHz TO 20MHz):
99MHz:
399MHz:
1.41ps
1.46ps
Figure 14. Absolute Phase Noise Using HSTL Driver,
SYSCLK = 1 GHz (SYSCLK PLL Driven by Rohde & Schwarz SMA100 Signal
Generator at 25 MHz )