Datasheet

AD9920A
Rev. B | Page 21 of 112
06878-023
t
DOUTINH
t
SHPINH
t
SHDINH
t
SHDINH
P[0]
CLI
RG
P[64] = P[0]
CCD
SIGNAL
P[32]P[16] P[48]POSITION
H2
RGr[0] RGf[16]
SHD
SHDLOC[0]
H1
H1r[0] H1f[32]
t
S1
SHP
SHPLOC[32]
DOUTPHASEP
50
62
1
12
t
S2
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
2. CERTAIN POSITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS.
3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE.
4. THE t
SHPINH
AREA FROM 50 TO 62 ONLY APPLIES IN SLAVE MODE.
5. THE t
SHDINH
AREA WILL APPLY TO EITHER H1 RISING OR FALLING EDGE, DEPENDING ON THE VALUE OF THE
H1HBLK MASKING POLARITY.
6. THE t
SHDINH
AREA CAN ALSO BE CHANGED TO A t
SHPINH
AREA IF THE H1HBLKRETIME BIT = 1.
Figure 23. High Speed Timing Default Locations
P[0]
RG
P[64] = P[0]
CCD
SIGNAL
P[32]P[16] P[48]TAP POSITION
PHASE 1
RGr[0] RGf[16]
SHD
SHDLOC[0]
HL
HLr[0] HLf[32]
t
S1
SHP
SHPLOC[32]
PHASE 2
PHASE 3
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN USING 3-PHASE HBLK MODE.
2. THE RISING EDGE OF EACH HCLK PHASE HAS AN ASSOCIATED SHDINH.
3. WHEN THE HBLK RETIME BITS (0x35 [3:0]) ARE ENABLED, THE INHIBITED AREA BECOMES SHPINH.
4. WHEN THE HBLK MASK LEVEL FOR PHASE 1, 2, OR 3 IS CHANGED TO LOW, THE INHIBIT AREA IS
REFERENCED TO THE HCLK FALLING EDGE, INSTEAD OF THE HCLK RISING EDGE.
06878-024
SHDINH/SHPINH
SHDINH/SHPINH
SHDINH/SHPINH
Figure 24. High Speed Timing Typical Locations, 3-Phase HCLK Mode