Datasheet

AD9920A
Rev. B | Page 80 of 112
VH SUPPLY
VL SUPPLY
SERIAL
WRITES
VD
(INPUT)
HD
(INPUT)
H-CLOCKS
CLOCKS ACTIVE WHEN OUT_CONTROL
REGISTER UPDATED AT VD/HD EDGE
H2, H4, H6, H8
H1, H3, H5, H7, RG
1
256
+1.8V SUPPLY
+3V SUPPLIES
VDR_EN
4
SYNC/RST
7
V1 TO V16
(V-DRIVER OUTPUT)
100µs500µs
VM
VH
XV1 TO XV24
XSUBCK
(INTERNAL)
VM SUPPLY
3
8
10
9
VDD
11
12
POWER
SUPPLIES
CLI
(INPUT)
0V
0V
LOW BY
DEFAULT
HIGH-Z BY
DEFAULT
V-DRIVER OUTPUTS ACTIVE
WHEN VDR_EN IS HIGH
VL (SUBCK ONLY)
06878-102
Figure 102. Recommended Power-Up Sequence and Synchronization, Master Mode