Datasheet

AD9920A
Rev. B | Page 82 of 112
0V
1
VM
VH
VDD
567 10 9 11
4
32 8
12
SERIAL
WRITES
VD
(INPUT)
HD
(INPUT)
H-CLOCKS
VDR_EN
V1 TO V16
(V-DRIVER OUTPUT)
XV1 TO XV24
XSUBCK
(INTERNAL)
POWER
SUPPLIES
CLI
(INPUT)
CLOCKS ACTIVE WHEN OUT_CONTROL
REGISTER UPDATED AT VD/HD EDGE
H2, H4, H6, H8
H1, H3, H5, H7, RG
V-DRIVER OUTPUTS ACTIVE
WHEN VDR_EN IS HIGH
VL (SUBCK ONLY)
LOW BY
DEFAULT
HIGH-Z BY
DEFAULT
100µs
500µs
0V
VH SUPPLY
VL SUPPLY
+1.8V SUPPLY
+3V SUPPLIES
VM SUPPLY
06878-103
SYNC/RST
Figure 103. Recommended Power-Up Sequence and Synchronization, Slave Mode