Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9923ABBCZ

CCD Signal Processor with V-Driver and

Precision Timing Generator

AD9923A

Rev. A

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Tel: 781.329.4700 www.analog.com

FEATURES

Integrated 15-channel V-driver

12-bit, 36 MHz analog-to-digital converter (ADC)

Similar register map to the AD9923

5-field, 10-phase vertical clock support

Complete on-chip timing generator

Precision Timing core with <600 ps resolution

Correlated double sampler (CDS)

6 dB to 42 dB 10-bit variable gain amplifier (VGA)

Black level clamp with variable level control

On-chip 3 V horizontal and RG drivers

2-phase and 4-phase H-clock modes

Electronic and mechanical shutter support

On-chip driver for external crystal

On-chip sync generator with external sync input

8 mm × 8 mm CSP_BGA package with 0.65 mm pitch

APPLICATIONS

Digital still cameras

GENERAL DESCRIPTION

The AD9923A is a complete 36 MHz front-end solution for

digital still cameras and other CCD imaging applications.

Similar to the AD9923 product, the AD9923A includes the

analog front end (AFE), a fully programmable timing generator

(TG), and a 15-channel vertical driver (V-driver). A Precision

Timing™core allows adjustment of high speed clocks with

approximately 600 ps resolution at 36 MHz operation.

The on-chip V-driver supports up to 15 channels for use with

5-field, 10-phase CCDs.

The analog front end includes black level clamping, CDS, VGA,

and a 12-bit ADC. The timing generator and V-driver provide

all the necessary CCD clocks: RG, H-clocks, vertical clocks, sensor

gate pulses, substrate clock, and substrate bias control. The

internal registers are programmed using a 3-wire serial

interface.

Packaged in an 8 mm × 8 mm CSP_BGA, the AD9923A is

specified over an operating temperature range of −25°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

AD9923A

DCLK

CLAMP

D0 TO D11

CCDIN

12-BIT

ADC

–3dB, 0dB, +3dB, +6dB

CDS

REFT REFB

VREF

+6dB TO +42dB

VGA

HORIZONTAL

DRIVERS

H1 TO H4

INTERNAL

REGISTERS

SDI

SCK

SYNC

GENERATOR

PRECISION

TIMING

GENERATOR

INTERNAL CLOCKS

VD SYNC CLI CLOVSUB, MSHUT,

STROBE

SUBCK

VERTICAL

TIMING

CONTROL

V-DRIVER

V1, V2, V3,

4, V5A, V5B,

6, V7A, V7B,

V8, V9, V10,

V11, V12, V13

XSUBCK,

XSUBCNT

XSG1 TO

XSG8

XV1 TO

XV13

05586-001

Figure 1.

Summary of content (84 pages)

PAGE 1
CCD Signal Processor with V-Driver and Precision Timing Generator AD9923A FEATURES GENERAL DESCRIPTION Integrated 15-channel V-driver 12-bit, 36 MHz analog-to-digital converter (ADC) Similar register map to the AD9923 5-field, 10-phase vertical clock support Complete on-chip timing generator Precision Timing core with <600 ps resolution Correlated double sampler (CDS) 6 dB to 42 dB 10-bit variable gain amplifier (VGA) Black level clamp with variable level control On-chip 3 V horizontal and RG drivers 2-ph
PAGE 2
AD9923A TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 14 Applications ....................................................................................... 1 Precision Timing High Speed Timing Generation ................. 15 General Description .........................................................................
PAGE 3
AD9923A SPECIFICATIONS Table 1.
PAGE 4
AD9923A DIGITAL SPECIFICATIONS DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted. Table 2. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage Conditions/Comments Powered by DVDD, DRVDD At IOH = 2 mA At IOL = 2 mA Symbol Min Typ VIH VIL IIH IIL CIN 2.1 VOH VOL DVDD − 0.5, DRVDD − 0.5 Max 0.6 10 10 10 0.
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AD9923A Conditions/Comments Symbol tPMH tPHM tPML Min Typ 25 30 25 Max Unit ns ns ns tRLH tRLM tRMH 40 45 30 ns ns ns tFHL tFHM tFML 40 90 25 ns ns ns 20 12 12 20 mA mA mA mA Ω 35 V-DRIVER INPUT 50% 50% tRLM, tRMH, tRLH V-DRIVER OUTPUT 90% 10% tPML, tPHM , tPHL 90% tPLM, tPMH, tPLH 10% tFML, tFHM, tFHL 05586-002 Parameter VMM to VH VH to VMM VMM to VLL Rise Time VLL to VH VLL to VMM VMM to VH Fall Time VH to VLL VH to VMM VMM to VLL Output Currents at −7.25 V at −0.25 V at +0.
PAGE 6
AD9923A Parameter BLACK LEVEL CLAMP Clamp Level Resolution Minimum Clamp Level (Code 0) Maximum Clamp Level (Code 1023) ANALOG-TO-DIGITAL CONVERTER (ADC) Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Low Gain (VGA Code 15) Maximum Gain (VGA Code 1023) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) 1 Conditions/Comments
PAGE 7
AD9923A Parameter SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read INHIBIT REGION FOR SHP AND SHD WITH RESPECT TO H-CLOCK EDGE LOCATION HxMASK = 0, HxRETIME = 0, HxPOLARITY = 0 1 2 Conditions/Comments Symbol tDH tDV Min 10 10 tSHDINH HxMASK = 0, HxRETIME = 0, HxPOLARITY = 1 Typ Max Unit ns ns HxPOS − 9 HxPOS − 18 tSHDINH HxNEG − 9 HxNEG − 18 HxMASK = 0, HxRETIME = 1, HxPOLARITY = 0 tSHPINH HxPOS − 7 HxPOS − 16 HxMASK = 0, HxRETIME = 1, HxPOLARITY = 1 tSHPINH HxN
PAGE 8
AD9923A ABSOLUTE MAXIMUM RATINGS Table 7. Parameter AVDD TCVDD HVDD RGVDD DVDD DRVDD VDD1, VDD2 VH1, VH2 VH1, VH2 VL1, VL2 VM1, VM2 VLL VMM VDR_EN V1 to V15 RG Output H1 to H4 Output Digital Outputs Digital Inputs SCK, SL, SDATA REFT/REFB, CCDIN Junction Temperature Lead Temperature, 10 sec To AVSS TCVSS HVSS RGVSS DVSS DRVSS VSS1, VSS2 VL1, VL2 VSS1, VSS2 VSS1, VSS2 VSS1, VSS2 VSS1, VSS2 VSS1, VSS2 VSS1, VSS2 VSS1, VSS2 RGVSS HVSS DVSS DVSS DVSS AVSS Rating −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.
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AD9923A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9923A TOP VIEW (Not to Scale) A1 CORNER INDEX AREA 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H L 05586-004 J K Figure 4. 105-Lead CSPBGA Package Pin Configuration Table 9. Pin Function Descriptions Pin No.
PAGE 10
AD9923A Pin No.
PAGE 11
AD9923A TYPICAL PERFORMANCE CHARACTERISTICS 450 5 400 4 3.3V 350 3 3.0V 2 INL (LSB) 250 2.7V 200 1 0 150 –1 100 –2 50 27 36 FREQUENCY (MHz) –3 05586-089 0 18 0 500 1000 1500 2000 2500 3000 3500 4000 CODE Figure 5. Power vs. Sample Rate 05586-087 POWER (V) 300 Figure 7. Typical INL Performance 0.6 55 50 0.4 +6dB 45 40 NOISE LSB (rms) 0 –0.2 35 +3dB 30 –3dB 25 20 15 0dB 10 –0.4 0 500 1000 1500 2000 2500 3000 CODE 3500 4000 Figure 6.
PAGE 12
AD9923A EQUIVALENT CIRCUITS HVDD OR RGVDD RG, HL, H1 TO H4 AVDD R 05586-008 AVSS AVSS OUTPUT 05586-005 THREE-STATE HVSS OR RGVSS Figure 12. HL, H1 to H4, and RG Drivers Figure 9. CCDIN, CCDGND DVDD DRVDD VDVDD DATA 3.5kΩ VDR_EN THREE-STATE D[0:11] VDVSS DVSS DRVSS 05586-006 Figure 13. VDR_EN Input Figure 10. Digital Data Outputs DVDD DVSS 05586-007 330Ω Figure 11. Digital Inputs Rev.
PAGE 13
AD9923A TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. Integral Nonlinearity (INL) The deviation of each code measured from a true straight line between the zero and full-scale values.
PAGE 14
AD9923A THEORY OF OPERATION Figure 15 and Figure 16 show the maximum horizontal and vertical counter dimensions for the AD9923A. Internal horizontal and vertical clocking is controlled by these counters to specify line and pixel locations. The maximum HD length is 8192 pixels per line, and the maximum VD length is 4096 lines per field. The H-drivers for HL, H1 to H4, and RG are included in the AD9923A, allowing these clocks to be directly connected to the CCD. An H-driver voltage, HVDD, of up to 3.
PAGE 15
AD9923A PRECISION TIMING HIGH SPEED TIMING GENERATION The AD9923A generates high speed timing signals using the flexible Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE. It consists of the reset gate (RG), horizontal drivers (H1 to H4 and HL), and sample clocks (SHP and SHD).
PAGE 16
AD9923A Table 11. Precision Timing Edge Locations Quadrant I II III IV Edge Location (Decimal) 0 to 11 12 to 23 24 to 35 36 to 47 POSITION P[0] P[12] Register Value (Decimal) 0 to 11 16 to 27 32 to 43 48 to 59 P[24] P[36] Register Value (Binary) 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 P[48] = P[0] CLI tCLIDLY 1 PIXEL PERIOD 05586-016 NOTES 1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCK. 2.
PAGE 17
AD9923A CCD SIGNAL RG HL/H1/H3 05586-018 H2/H4 NOTES 1. USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING. Figure 19. 2-Phase H-Clock Operation POSITION P[0] P[12] RGr[0] RGf[12] P[24] P[36] P[48] = P[0] PIXEL PERIOD RG Hr[0] Hf[24] HL/H1/H3 H2/H4 SHP[24] tS1 CCD SIGNAL SHD[48] 05586-019 NOTES 1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. 2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN. Figure 20.
PAGE 18
AD9923A CLI tCLIDLY N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N CCDIN SAMPLE PIXEL N SHD (INTERNAL) ADC DOUT (INTERNAL) N–17 N–16 N–15 N–14 N–13 N–12 N–11 N–10 N–9 N–8 tDOUTINH DCLK PIPELINE LATENCY = 16 CYCLES N–17 N–16 N–15 N–14 N–13 N–12 N–11 N–10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 NOTES 1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0. 2.
PAGE 19
AD9923A Table 12.
PAGE 20
AD9923A Individual HBLK Patterns The HBLK programmable timing shown in Figure 26 is similar to CLPOB and PBLK; however, there is no start polarity control. Only the toggle positions are used to designate the start and end positions of the blanking period. Additionally, there is a polarity control register, HBLKMASK, that designates the polarity of the horizontal clock signals during the blanking period. Setting HBLKMASK high sets H1 = H3 = high and H2 = H4 = low during blanking, as shown in Figure 27.
PAGE 21
AD9923A ... HD ... HBLK HL/H1/H3 THE POLARITY OF HL/H1/H3 DURING BLANKING ARE INDEPENDENTLY PROGRAMMABLE (H2/H4 IS OPPOSITE POLARITY OF H1/H3). 05586-025 H1/H3 H2/H4 Figure 27. HBLK Masking Polarity Control HBLKTOGE2 HBLKTOGE1 HBLKTOGE4 HBLKTOGE3 HBLKTOGE6 HBLKTOGE5 HBLK HL/H1/H3 SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS (HBLKALT = 0). 05586-026 H2/H4 Figure 28.
PAGE 22
AD9923A HD ODD LINE HBLKTOGE1 EVEN LINE HBLKTOGE4 HBLKTOGE6 HBLKTOGE3 HBLKTOGE5 HBLKTOGE2 HBLK HL/H1/H3 05586-027 H2/H4 ALTERNATING H-BLANK PATTERN USING HBLKALT = 1 MODE. Figure 29. HBLK Odd/Even Alternation Using HBLKALT = 1 HD ODD LINE EVEN LINE HBLKTOGE4 HBLKTOGE6 HBLKTOGE3 HBLKTOGE5 HBLKTOGE2 HBLKTOGE1 HBLK HL/H1/H3 05586-028 H2/H4 ALTERNATING H-BLANK PATTERN USING HBLKALT = 2 MODE. Figure 30.
PAGE 23
AD9923A Increasing H-Clock Width During HBLK The AD9923A allows the H1 to H4 pulse width to be increased during the HBLK interval. The H-clock pulse width can increase by reducing the H-clock frequency (see Table 14). The HBLKWIDTH register (Register 0x35, Bits[6:4]) is a 3-bit register that allows the H-clock frequency to be reduced by 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, or 1/14. The reduced frequency only occurs for H1 to H4 pulses that are located within the HBLK area.
PAGE 24
AD9923A VERTICAL TIMING GENERATION 3. Construct the readout for an entire field by dividing the field into regions and assigning a sequence to each region. Each field can contain up to nine regions to accommodate different steps, such as high speed line shifts and unique vertical line transfers, of the readout. The total number of V-patterns, V-sequences, and fields are programmable and limited by the number of registers.
PAGE 25
AD9923A Vertical Pattern (VPAT) Groups A vertical pattern (VPAT) group defines the individual pulse pattern for each XV1 to XV13 output signal. Table 15 summarizes the registers that are available for generating each VPAT group. The first, second, third, fourth, fifth, and sixth toggle positions (XVTOG1, XVTOG2, XVTOG3, XVTOG4, XVTOG5, XVTOG6) are the pixel locations where the pulse transitions. All toggle positions are 13-bit values that can be placed anywhere in the horizontal line.
PAGE 26
AD9923A Generating Line Alternation for V-Sequences and HBLK section). The VSTARTA and VSTARTB registers specify the pixel location where the V-pattern group starts. The VMASK register is used in conjunction with the FREEZE/RESUME registers to enable optional masking of the XV outputs. Either or both of the FREEZE1/RESUME1 and FREEZE2/RESUME2 registers can be enabled.
PAGE 27
AD9923A Table 16.
PAGE 28
AD9923A Group A/Group B Selection The AD9923A has the flexibility to use two V-pattern groups in a vertical sequence. In general, all vertical outputs use the same V-pattern group during a sequence, but some outputs can be assigned to a different V-pattern group. This is useful during certain CCD readout modes. The GROUPSEL register is used to select Group A or Group B for each XV output (the LSB is XV1, the MSB is XV13). Setting each bit to 0 selects Group A; setting each bit to 1 selects Group B.
PAGE 29
AD9923A Generating Line Alternation for V-Sequences and HBLK During low resolution readout, some CCDs require a different number of vertical clocks on alternate lines. The AD9923A can support such CCDs by using different VREP registers. This allows a different number of VPAT repetitions to be programmed on odd and even lines. Note that only the number of repeats is different in odd and even lines, but the VPAT group remains the same. There are separate controls for the assigned Group A and Group B patterns.
PAGE 30
AD9923A which point the signals continue with any remaining toggle positions. Masking Using Freeze/Resume Registers As shown in Figure 42 and Figure 43, the FREEZE/RESUME registers are used to temporarily mask the XV outputs. The pixel locations to start (FREEZE) and end (RESUME) the masking create an area in which the vertical toggle positions are ignored. At the pixel location specified in the FREEZE register, the XV outputs are held static at their current dc state, high or low.
PAGE 31
AD9923A Hold Area Using FREEZE/RESUME Registers The FREEZE/RESUME registers can also be used to create a hold area, in which the XV outputs are temporarily held and then later resume at the point where they were held. As shown in Figure 44, this is different than using the VMASK register, HD FREEZE because the XV outputs continue from where they stopped (as opposed to having the pixel counter run continuously), with any toggle positions that fall between the FREEZE and RESUME locations being ignored.
PAGE 32
AD9923A Complete Field: Combining V-Sequences After the V-sequences are created, they are combined to create different readout fields. A field consists of up to nine regions. Within each region, a different V-sequence can be selected. Figure 46 shows how the sequence change position (SCP) registers designate the line boundary for each region and how the VSEQSEL registers select the V-sequence for each region. Registers to control the VSG outputs are also included in the field registers.
PAGE 33
AD9923A SCP 0 SCP 1 SCP 2 SCP 3 SCP 4 SCP 5 SCP 8 VD REGION 0 REGION 1 REGION 2 REGION 3 REGION 4 REGION 8 VSEQSEL0 VSEQSEL1 VSEQSEL2 VSEQSEL3 VSEQSEL4 VSEQSEL8 HD XV1 TO XV13 SGACTLINE VSG 05586-045 FIELD SETTINGS: 1. SEQUENCE CHANGE POSITIONS (SCP1 TO SCP8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD. 2. VSEQSEL0 TO VSEQSEL8 SELECTS THE DESIRED V-SEQUENCE FOR EACH REGION. 3. SGLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD CONTAINS THE SENSOR-GATE PULSE(S). Figure 46.
PAGE 34
AD9923A START POSITION FOR SECOND VPAT GROUP USES VSTARTSECOND REGISTER HD VSG XV1 XV2 05586-046 XV13 SECOND VPAT GROUP Figure 47. Example of Second VPAT Group During Sensor Gate Line VD HD SCP 1 LINE 0 LINE 1 SCP 2 LINE 2 LINE 24 LINE 25 REGION 0 REGION 1: SWEEP REGION REGION 2 05586-047 XV1 TO XV13 Figure 48. Example of Sweep Region for High Speed Vertical Shift Figure 48 shows an example of sweep mode operation.
PAGE 35
AD9923A Table 19.
PAGE 36
AD9923A Vertical Sensor Gate (Shift Gate) Patterns In an interline CCD, the vertical sensor gates (VSG) are used to transfer the pixel charges from the light sensitive image area into the light shielded vertical registers. From the light shielded vertical registers, the image is then read line by line using the XV1 to XV13 vertical transfer pulses in conjunction with the high speed horizontal clocks. Table 20 summarizes the VSG pattern registers. The AD9923A has eight VSG outputs, VSG1 to VSG8.
PAGE 37
AD9923A MODE Register The MODE register is a single register that selects the field timing of the AD9923A. Typically, all field, V-sequence, and V-pattern group information is programmed into the AD9923A at startup. During operation, the MODE register allows the user to select any combination of field timing to meet the current requirements of the system. Using the MODE register in conjunction with preprogrammed timing greatly reduces the system programming requirements during camera operation.
PAGE 38
AD9923A VERTICAL TIMING EXAMPLE Region 0 To better understand how the AD9923A vertical timing generation is used, consider the example CCD timing chart in Figure 52. It illustrates a CCD using a general three-field readout technique. As described in the Complete Field: Combining V-Sequences section, each readout field should be divided into separate regions to perform each step of the readout. The sequence change position (SCP) registers determine the line boundaries for each region.
PAGE 39
Rev. A | Page 39 of 84 CCD OUT VSUB MSHUT SUBCK XV6 XV5 XV4 XV3 XV2 XV1 HD VD OPEN REGION 0 CLOSED Figure 52.
PAGE 40
AD9923A VERTICAL DRIVER SIGNAL CONFIGURATION VDR_EN = low, V1 to V13 are forced to VM and SUBCK is forced to VLL. The VDR_EN pin takes priority over the XV and VSG signals coming from the timing generator. As shown in Figure 53, XV1 to XV13, VSG1 to VSG8, and XSUBCK are outputs from the internal AD9923A timing generator, and V1 to V13 and SUBCK are the resulting outputs from the AD9923A vertical driver.
PAGE 41
AD9923A Table 28. V11 Output Polarity Table 22. V1 Output Polarity XV1 L L H H Vertical Driver Input VSG1 L H L H V1 Output VH VM VL VL Table 23. V3 Output Polarity XV3 L L H H Vertical Driver Input VSG3 L H L H XV5 L L H H V3 Output VH VM VL VL Vertical Driver Input VSG6 L H L H V5A Output VH VM VL VL V5B Output VH VM VL VL XV7 L L H H V7A Output VH VM VL VL Table 27.
PAGE 42
AD9923A Table 35. V10 Output Polarity Vertical Driver Input XV10 L H Table 37. SUBCK Output Polarity V10 Output VM VL Table 36. V13 Output Polarity Vertical Driver Input XV13 L H V13 Output VM VL XSUBCK L L H H Vertical Driver Input XSUBCNT L H L H SUBCK Output VH VH VMM VLL XV1 VSG1 VH VM 05586-053 V1 VL Figure 54. XV1, VSG1, and V1 Output Polarities XV11 VSG2 VH VM 05586-054 V11 VL Figure 55. XV11, VSG2, and V11 Output Polarities XV3 VSG3 VH VM 05586-055 V3 VL Figure 56.
PAGE 43
AD9923A XV12 VSG4 VH VM 05586-056 V12 VL Figure 57. XV12, VSG4, and V12 Output Polarities XV5 VSG5 VH VM 05586-057 V5A VL Figure 58. XV5, VSG5, and V5A Output Polarities XV5 VSG6 VH VM 05586-058 V5B VL Figure 59. XV5, VSG6, and V5B Output Polarities XV7 VSG7 VH VM 05586-059 V7A VL Figure 60. XV7, VSG7, and V7A Output Polarities Rev.
PAGE 44
AD9923A XV7 VSG8 VH V7B 05586-060 VM VL Figure 61. XV7, VSG8, and V7B Output Polarities XV2, XV4, XV6, XV8 XV9, XV10, XV13 05586-061 VM V2, V4, V6, V8 V9, V10, V13 VL Figure 62. XV2, XV4, XV6, XV8, XV9, XV10, XV13 and V2, V4, V6, V8, V9, V10, V13 Output Polarities XSUBCNT XSUBCK VH VMM 05586-062 SUBCK VLL Figure 63.
PAGE 45
AD9923A SUBCK: Normal Operation Table 38.
PAGE 46
AD9923A VD HD VSG tEXP tEXP SUBCK 05586-063 SUBCK PROGRAMMABLE SETTINGS: 1. PULSE POLARITY USING THE SUBCKPOL REGISTER. 2. NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER (SUBNUM = 3 IN THE ABOVE EXAMPLE). 3. PIXEL LOCATION OF PULSE WITHIN THE LINE AND PULSE WIDTH PROGRAMMED USING THE SUBCK1TOG REGISTER. Figure 64. Normal Shutter Mode VD HD VSG tEXP tEXP NOTES 1. SECOND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE. 2.
PAGE 47
AD9923A SUBCK: Suppression Normally, the SUBCK begins pulsing on the line following the sensor gate line (VSG). Some CCDs require suppressing the SUBCK pulse for one or more lines following the VSG line. The SUBCKSUPPRESS register enables such suppression. Readout After Exposure After the exposure, the readout of the CCD data occurs, beginning with the sensor gate (VSG) operation. By default, the AD9923A generates VSG pulses in every field.
PAGE 48
AD9923A Table 39.
PAGE 49
AD9923A Table 40 shows the register parameters for controlling the SHUT signals. There are three different ways to use the SHUT signals: automatic trigger, single trigger, and manual control. trigger mode if they, and an exposure operation, have been triggered. Automatic Trigger Any SHUT signal can be controlled in manual control mode, instead of using the TRIGGER register to activate it.
PAGE 50
AD9923A SINGLE TRIGGER WRITE VD VSG ON STATE OFF STATE 2 3 SHUT PROGRAMMABLE SETTINGS: 1ACTIVE POLARITY. DEFINES THE LOGIC LEVEL DURING ON TIME. ABOVE EXAMPLE USES ACTIVE POLARITY = 1. 2ON POSITION IS PROGRAMMABLE TO ANY LINE/PIXEL IN FIELD IMMEDIATELY FOLLOWING SINGLE TRIGGER WRITE. 3OFF POSITION IS PROGRAMMABLE TO ANY LINE/PIXEL IN FIELD IMMEDIATELY FOLLOWING SINGLE TRIGGER WRITE. 05586-067 SHUT0 TO SHUT3 1 Figure 68.
PAGE 51
AD9923A Table 40. VSUB0 to VSUB1 and SHUT0 to SHUT3 Register Parameters Register VSUB_CTRL Length (Bits) 3 Range 0 to 7 MSHUT_CTRL 3 0 to 7 STROBE_CTRL 3 0 to 7 TESTO_CTRL 3 0 to 7 VSUB0_MUX 1 High/low VSUB1_MUX 1 High/low SHUT1_SHUT2_MUX 1 High/low VSUB_MODE 1b High/low VSUB_KEEPON VSUB_ON VSUBPOL SHUT_ON 1 12 1 1 High/low 0 to 4095 line location High/low On/off SHUTPOL 1 High/low Description Selects which internal shutter signal is mapped to the VSUB pin. 0: SHUT0. 1: SHUT1.
PAGE 52
AD9923A Register SHUT_MAN Length (Bits) 1 Range Enable/disable SHUT_ON_FD SHUT_ON_LN SHUT_ON_PX SHUT_OFF_FD SHUT_OFF_LN SHUT_OFF_PX 12 12 13 12 12 13 0 to 4095 field location 0 to 4095 line location 0 to 8191 pixel location 0 to 4095 field location 0 to 4095 line location 0 to 8191 pixel location Explanation of Figure 71 Description Enables SHUT manual control mode. 0 = disable. 1 = enable. Field location to switch on MSHUT. Inactive, or closed. Line position to switch on MSHUT. Inactive, or closed.
PAGE 53
Rev. A | Page 53 of 84 CCD OUT VSUB (VSUB0) MECHANICAL SHUTTER MSHUT (SHUT1) STROBE (SHUT0) SUBCK VSG VD SERIAL WRITES DRAFT IMAGE 1 2 MODE 0 DRAFT IMAGE 3 4 tEXP CLOSED MODE 1 OPEN 5 6 STILL IMAGE FIRST FIELD 7 STILL IMAGE SECOND FIELD STILL IMAGE READOUT 8 9 STILL IMAGE THIRD FIELD 10 10 10 10 OPEN DRAFT IMAGE AD9923A EXAMPLE OF EXPOSURE AND READOUT OF INTERLACED FRAME Figure 71.
PAGE 54
AD9923A FG_TRIG OPERATION and pixel resolution. The field registers for SHUT1 are ignored because the field placement of the FG_TRIG pulse is matched to the field count specified by the MODE register operation. The FG_TRIGEN register contains a three-bit value that specifies which field count contains the FG_TRIG pulse. Figure 72 shows how the FG_TRIG pulse is generated using these registers.
PAGE 55
AD9923A 0.1µF 0.1µF REFB REFT 1.0V 2.0V INTERNAL VREF 1.5V SHP 0.1µF CCDIN FIXED DELAY CLI DC RESTORE SHD 0 DOUT DLY 12-BIT ADC VGA GAIN REGISTER DCLK DOUT PHASE DCLK MODE 2V FULL SCALE 6dB ~ 42dB VGA CDS 1 DAC OUTPUT DATA LATCH 12 DOUT OPTICAL BLACK CLAMP CLPOB PBLK DIGITAL FILTER SHP DOUT SHD PHASE CLPOB PBLK 8 CLAMP LEVEL REGISTER PRECISION TIMING GENERATION V-H TIMING GENERATION AD9923A 05586-071 CLI Figure 73.
PAGE 56
AD9923A Optical Black Clamp The optical black clamp loop removes residual offsets in the signal chain and tracks low frequency variations in the CCD black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a fixed black level reference, selected by the user in the CLAMPLEVEL register. The value can be programmed between 0 LSB and 255 LSB in 1023 steps.
PAGE 57
AD9923A 10. OUTCONTROL to enable all outputs. If an external SYNC pulse is not available, generate an internal SYNC pulse by writing to the SYNCPOL register as described in the Generating Software Sync Without External Sync Signal section. Generate a SYNC event. If SYNC is high at power-up, bring SYNC input low for a minimum of 100 ns. Then, bring SYNC high. This causes the internal counters to reset and starts a VD/HD operation.
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AD9923A SYNC VD SUSPEND HD NOTES 1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0. 2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13). 3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x14). 4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUTCONTROL = LOW. 5. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
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AD9923A VD HD 3ns MIN CLI tCLIDLY 3ns MIN SHD INTERNAL HD INTERNAL H-COUNTER (PIXEL COUNTER) X H-COUNTER RESET 32.5 CYCLES X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 2 05586-075 NOTES 1. INTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE. 2. INTERNAL H-COUNTER IS ALWAYS RESET 32.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE. 3.
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AD9923A STANDBY[1:0] = 01 = Standby 1 mode to hold a specific value during the Standby 3 mode using Register 0xE2, as detailed in Table 44. The vertical outputs can be programmed to hold a specific value when OUTCONTROL = low, or when in Standby 1 or Standby 2 mode, by using Register 0xF3. The following list provides guidelines for the mapping of the bits in these registers to the various vertical and shutter outputs when the device is in one of the three standby modes, or when OUTCONTROL = low.
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AD9923A Table 44.
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AD9923A mutual inductance, route the complementary signals, H1 and H2, as symmetrically and close together as possible. The same should be done for the H3 and H4 signals. Heavier PCB traces are recommended because of the large transient current demand placed by the CCD on HL and H1 to H4. If possible, physically locating the AD9923A closer to the CCD reduces the inductance on these lines. The routing path should be as direct as possible from the AD9923A to the CCD.
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AD9923A 3 SERIAL INTERFACE (FROM ASIC/DSP) SYNC (FROM ASIC/DSP) VERTICAL SYNC (TO/FROM ASIC/DSP) MASTER CLOCK INPUT HORIZONTAL SYNC (TO/FROM ASIC/DSP) OPTIONAL CLOCK OSCILLATOR OUTPUT (FOR CRYSTAL APPLICATION) RESETB (FROM ASIC/DSP) DCLK OUTPUT 12 VSUB OUTPUT (TO CCD BIAS CIRCUIT) STROBE CONTROL OUTPUT L8 L7 MSHUT STROBE VSUB K6 G5 F5 CLO CLI A8 A9 SDI B1 SCK SL C3 C2 SYNC HD VD E2 D2 G7 RSTB E5 D0 (LSB) DCLK F1 H3 G1 D4 D3 D2 D1 H1 H2 D5 J2 J3 D7 D6 J1 K3 K1 K2 E6 G2
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AD9923A 3 SERIAL INTERFACE (FROM ASIC/DSP) VERTICAL SYNC (TO/FROM ASIC/DSP) MASTER CLOCK INPUT HORIZONTAL SYNC (TO/FROM ASIC/DSP) OPTIONAL CLOCK OSCILLATOR OUTPUT (FOR CRYSTAL APPLICATION) RESETB (FROM ASIC/DSP) DCLK OUTPUT 12 VSUB OUTPUT (TO CCD BIAS CIRCUIT) DATA OUTPUTS DVDD2 DVDD2 L8 L7 MSHUT STROBE G5 F5 VSUB K6 CLO A9 A8 CLI SDI SCK C3 C2 B1 SL SYNC HD VD RSTB E5 F1 E2 D2 G7 DCLK D0 (LSB) H3 G1 D4 D3 D2 D1 H1 H2 D5 J2 J3 J1 D7 D6 K3 D10 D9 D8 K1 K2 E6 G2 B9 G
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AD9923A SERIAL INTERFACE TIMING with 0s during the serial write operation. If fewer than 28 data bits are written, the register is not updated with new data. All of the AD9923A internal registers are accessed through a 3-wire serial interface. Each register consists of a 12-bit address and a 28-bit data-word. Both the address and data-word are written by starting with the LSB. To write to each register, a 40-bit operation is required, as shown in Figure 84.
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AD9923A LAYOUT OF INTERNAL REGISTERS The AD9923A address space is divided into two register areas, as illustrated in Figure 86. In the first area, Address 0x00 to Address 0x91 contain the registers for the AFE, miscellaneous functions, VD/HD parameters, timing core, CLPOB masking, SG patterns, shutter functions, and memory configuration. The second area of the address space, beginning at Address 0x400, consists of the registers for the V-pattern groups, V-sequences, and fields.
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AD9923A • UPDATING NEW REGISTER VALUES SCP Updated—All V-pattern and V-sequence registers are updated at the next SCP where they are used. For example, in Figure 88, this field has selected Region 1 to use VSequence 3 for the vertical outputs; therefore, a write to a V-Sequence 3 or V-pattern group register, which is referenced by V-Sequence 3, is updated at SCP 1. If there are multiple writes to the same register, only the last one before SCP1 is updated.
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AD9923A COMPLETE REGISTER LISTING When an address contains less than 28 data bits, all remaining bits must be written as 0s. Table 46. AFE Registers Address (Hex) 00 Data Bits [1:0] Default Value 3 Update Type SCK [2] 1 CLPENABLE [3] 0 CLPSPEED [4] 0 FASTUPDATE [5] 0 PBLK_LVL [6] 0 DCBYP [15:11] 0 XSUBCNT_MUX Name STANDBY Description Standby modes. 0: normal operation. 1: Standby 1 mode. 2: Standby 2 mode. 3: Standby 3 mode. 0: disable OB clamp. 1: enable OB clamp.
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AD9923A Address (Hex) 01 Data Bits [0] Default Value 0 Update Type SCK [1] 0 DOUTLATCH [2] 0 GRAYEN 04 [3] [1:0] 1 1 VD TEST CDSGAIN 05 06 [9:0] [9:0] F 1EC VD VD VGAGAIN CLAMPLEVEL Name DOUTDISABLE Description 0: data outputs are driven. 1: data outputs are three-stated. 0: latch data outputs using DOUT PHASE register setting. 1: output latch is transparent. 0: straight binary encoding of ADC digital output data. 1: enable gray encoding of ADC digital output data. Set to 1.
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AD9923A Table 47. Miscellaneous Registers Address (Hex) 10 Data Bits [0] Default Value 0 Update Type SCK Name SW_RST 11 [0] 0 VD OUTCONTROL 12 [0] 1 SCK SYNCENABLE [7:1] [9:8] 0 0 13 [0] 0 SCK SYNCPOL 14 [0] 0 SCK SYNCSUSPEND 15 [0] 0 SCK TGCORE_RSTB 16 [0] 0 SCK OSC_RST 17 0 0 0 SCK 18 [7:0] [8] [11:0] VD TEST1 TEST2 UPDATE 19 [0] 0 SCK PREVENTUP 1A [0] 0 VD GPO TEST OUTPUTPBLK Description Software reset. Bit resets to 0.
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AD9923A Table 49.
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AD9923A Address (Hex) 37 38 Data Bits [7:4] [11:8] [15:12] [19:16] [23:20] [5:0] [13:8] [5:0] [7:6] [8] Default Value 1 1 1 1 1 24 0 0 0 0 Update Type [10:9] 2 DOUTDELAY [11] 0 DCLKINV SCK SCK Name H2DRV H3DRV H4DRV HLDRV RGDRV SHPLOC SHDLOC DOUTPHASE Unused DCLKMODE Description H2 drive strength. H3 drive strength. H4 drive strength. HL drive strength. RG drive strength. SHP sample location. SHD sample location. DOUT (internal signal) phase control. Must be set to 0. DCLK mode.
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AD9923A Table 51.
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AD9923A Table 52. Shutter Control Registers Address (Hex) 60 61 Data Bits [2:0] Default Value 0 Update Type VD [5:3] 1 MSHUT_CTRL [8:6] 2 STROBE_CTRL [11:9] 3 TESTO_CTRL [7:0] 0 VD Name VSUB_CTRL TRIGGER Description Selects which internal signal is used for the VSUB output pin. 0: use SHUT0 parameters (Register 0x06D to Register 0x071). 1: use SHUT1 parameters (Register 0x072 to Register 0x076). 2: use SHUT2 parameters (Register 0x077 to Register 0x07B).
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AD9923A Address (Hex) Data Bits Default Value Update Type Name 62 63 [2:0] [11:0] 2 0 VD VD READOUTNUM EXPOSURENUM [12] 0 [11:0] [23:12] [1:0] 0 0 0 [0] [12:0] [25:13] [12:0] [25:13] [0] 1 1FFF 1FFF 1FFF 1FFF 0 [1] 0 [11:0] [12] [13] [0] 0 0 1 0 [1] 0 [11:0] [12] [13] [0] 0 0 1 0 [1] [2] 1 0 [11:0] [11:0] [12] [25:13] [11:0] 0 0 0 0 0 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 VDHDOFF SG SG SG SG SG VD SUBSUPPRESS SUBCKNUM SUBCKMASK SUBCKPOL SUBCK1TOG1 SUBCK1TOG2 SUBCK2TO
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AD9923A Address (Hex) 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 Data Bits [11:0] [12] [25:13] [0] Default Value 0 0 0 0 [1] [2] 1 0 [11:0] [11:0] [12] [25:13] [11:0] [11:0] [12] [25:13] [0] 0 0 0 0 0 0 0 0 0 [1] [2] 1 0 [11:0] [11:0] [12] [25:3] [11:0] [11:0] [12] [25:13] [0] 0 0 0 0 0 0 0 0 0 [1] [2] 1 0 [11:0] [11:0] [12] [25:13] [11:0] [11:0] [12] [25:13] 0 0 0 0 0 0 0 0 Update Type VD VD VD Name SHUT0_OFF_LN Unused SHUT0_OFF_PX SHUT1_ON SHUT1POL SHUT1_MAN VD VD VD VD VD
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AD9923A Table 53. Memory Configuration Registers Address (Hex) 90 91 Data Bits [4:0] [4:0] Default Value 0 0 Update VD VD Name VPAT_NUM VSEQ_NUM Description Total number of V-pattern groups. Total number of V-sequences. Table 54.
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AD9923A Address (Hex) F3 Data Bits [21:0] Default Value 3FE000 Update SCK Name STANDBY12POL Description Programmable polarities for V-outputs and XSUBCK during Standby 1, Standby 2, or if OUTCONTROL = low. [0] = XV1 polarity. [1] = XV2 polarity. [2] = XV3 polarity. [3] = XV4 polarity. [4] = XV5 polarity. [5] = XV6 polarity. [6] = XV7 polarity. [7] = XV8 polarity. [8] = XV9 polarity. [9] = XV10 polarity. [10] = XV11 polarity. [11] = XV12 polarity. [12] = XV13 polarity. [13] = VSG1 polarity.
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AD9923A Unused XV-channels must have toggle positions programmed to maximum values. For example, if XV1 to XV8 are used, XV9 to XV12 must have all toggle positions set to maximum values. This prevents unpredictable behavior because the default values are unknown. Table 56.
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AD9923A Address (Hex) 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 Data Bits [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [25:0] Default Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefi
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AD9923A Address (Hex) 01 02 03 04 05 06 Data Bits [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [12:0] [13] Default Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Update Type SCP [18:14] Und
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AD9923A Address (Hex) 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 Data Bits [12:0] Default Value Undefined Update Type SCP [25:13] Undefined [12:0] Undefined [25:13] Undefined [12:0] Undefined [25:13] Undefined [12:0] [25:13] [12:0] [25:13] [12:0] Undefined Undefined Undefined Undefined Undefined [25:13] Undefined [12:0] Undefined [20:13] Undefined HBLKREP [21] [22] [23] [12:0] [25:13] [12:0] [25:13] [25:0] [11:0] [12] [13] [25:0] [25:0] Undefined Undefined Undefined Undefined Undef
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AD9923A Table 58.
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AD9923A OUTLINE DIMENSIONS A1 BALL CORNER 8.10 8.00 SQ 7.90 11 10 9 8 7 6 5 4 3 2 1 A BALL A1 PAD CORNER B C D E F G 6.50 BSC SQ H J K L 0.65 BSC BOTTOM VIEW TOP VIEW DETAIL A DETAIL A 1.31 1.16 0.91 MIN 0.25 MIN 0.45 0.40 0.35 BALL DIAMETER SEATING PLANE COPLANARITY 0.10 *COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION TO PACKAGE HEIGHT. 080807-A *1.40 Figure 89.