Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9945KCPZ

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

Fax:

AD9945

Complete 12-Bit 40 MHz

CCD Signal Processor

FEATURES

40 MSPS Correlated Double Sampler (CDS)

6 dB to 40 dB 10-Bit Variable Gain Amplifier (VGA)

Low Noise Optical Black Clamp Circuit

Preblanking Function

12-Bit 40 MSPS A/D Converter

No Missing Codes Guaranteed

3-Wire Serial Digital Interface

3 V Single-Supply Operation

Low Power: mW @ 3 V Supply

Space-Saving 32-Lead 5 mm

ⴛ

5 mm LFCSP

APPLICATIONS

Digital Still Cameras

Digital Video Camcorders

PC Cameras

Portable CCD Imaging Devices

CCTV Cameras

FUNCTIONAL BLOCK DIAGRAM

DATACLKSHDSHP

BAND GAP

REFERENCE

DOUT

CCDIN

PBLK

REFT

REFB

INTERNAL

TIMING

6dB TO 40dB

AVDD

DVDD

DVSS

AVSS

DRVDD

DRVSS

DIGITAL

INTERFACE

SDATASCK

CLPOB

AD9945

CONTROL

REGISTERS

12-BIT

ADC

CLP

VGACDS

GENERAL DESCRIPTION

The AD9945 is a complete analog signal processor for CCD

applications. It features a 40 MHz single-channel architecture

designed to sample and condition the outputs of interlaced and

progressive scan area CCD arrays. The AD9945’s signal chain

consists of a correlated double sampler (CDS), a digitally con-

trolled variable gain amplifier (VGA), a black level clamp, and a

12-bit A/D converter.

The internal registers are programmed through a 3-wire serial digital

interface. Programmable features include gain adjustment, black

level adjustment, input clock polarity, and power-down modes.

The AD9945 operates from a single 3 V power supply, typi-

cally dissipates mW, and is packaged in a space-saving

32-lead LFCSP.

REV.

160

781/461-3113

Summary of content (14 pages)

PAGE 1
Complete 12-Bit 40 MHz CCD Signal Processor AD9945 FEATURES 40 MSPS Correlated Double Sampler (CDS) 6 dB to 40 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Optical Black Clamp Circuit Preblanking Function 12-Bit 40 MSPS A/D Converter No Missing Codes Guaranteed 3-Wire Serial Digital Interface 3 V Single-Supply Operation Low Power: 160 mW @ 3 V Supply Space-Saving 32-Lead 5 mm ⴛ 5 mm LFCSP GENERAL DESCRIPTION APPLICATIONS Digital Still Cameras Digital Video Camcorders PC Cameras Portable CCD Imaging D
PAGE 2
AD9945–SPECIFICATIONS GENERAL SPECIFICATIONS (T MIN to TMAX, AVDD = DVDD = DRVDD= 3.0 V, fSAMP = 40 MHz, unless otherwise noted.) Parameter Min TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver Typ Max Unit –20 –65 +85 +150 °C °C 2.85 3.6 V POWER CONSUMPTION Normal Operation (DRVDD Power not Included) DRVDD Power Only (CLOAD = 20 pF) Power-Down Mode MAXIMUM CLOCK RATE 160 mW mW mW 10 1.5 40 MHz Specifications subject to change without notice.
PAGE 3
AD9945 SYSTEM SPECIFICATIONS (T MIN to TMAX , AVDD = DVDD = DRVDD = 3.0 V, fSAMP = 40 MHz, Register 0xD = 0x838, unless otherwise noted.) Parameter Min CDS Maximum Input Range before Saturation* Allowable CCD Reset Transient* Maximum CCD Black Pixel Amplitude* VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Minimum Gain Maximum Gain Low Gain Mode 1024 Guaranteed 40.0 5.3 41.5 ¦1.5 0 Vp-p mV mV See Input Waveform in Footnote dB dB +1.
PAGE 4
AD9945 TIMING SPECIFICATIONS (C = 20 pF, f L SAMP = 40 MHz, CCD Mode Timing in Figures 8 and 9, Serial Timing in Figures 4 and 5.) Parameter Symbol Min SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK High/Low Pulse Width SHP Pulse Width SHD Pulse Width CLPOB Pulse Width* SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge Internal Clock Delay tCONV tADC tSHP tSHD tCOB tS1 tS2 tID 25 10 DATA OUTPUTS Output Delay Pipeline Delay 2 11.
PAGE 5
AD9945 32 31 30 29 28 27 26 25 D1 D0 NC NC NC SCK SDATA SL PIN CONFIGURATION 1 2 3 4 5 6 7 8 PIN 1 INDICATOR AD9945 TOP VIEW 24 23 22 21 20 19 18 17 REFB REFT CCDIN AVSS AVDD SHD SHP CLPOB D10 9 D11 10 DRVDD 11 DRVSS 12 DVDD 13 DATACLK 14 DVSS 15 PBLK 16 D2 D3 D4 D5 D6 D7 D8 D9 NOTES 1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE GROUND PLANE OF THE PCB.
PAGE 6
AD9945 at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship DEFINITIONS OF SPECIFICATIONS Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes must be present over all operating conditions.
PAGE 7
Typical Performance Characteristics–AD9945 1.0 180 0.5 VDD = 3.3 V 150 DNL (LSB) POWER DISSIPATION (mV) 165 VDD = 3.0 V 135 0 120 –0.5 105 90 25 32 SAMPLE RATE (MHz) –1.0 40 0 1600 2400 3200 CODE TPC 1. Power vs. Sampling Rate REV. C 800 TPC 2.
PAGE 8
AD9945 INTERNAL REGISTER DESCRIPTION Table I. Internal Register Map Register Name A3 A2 A1 A0 Address Bits Data Bits Function Operation 0 D0 D2, D1 D3 D5, D4 D6 Software Reset (0 = Normal Operation, 1 = Reset all registers to default) Power-Down Modes (00 = Normal Power, 01 = Standby, 10 = Total Shutdown) OB Clamp Disable (0 = Clamp ON, 1 = Clamp OFF) Test Mode. Should always be set to 00.
PAGE 9
AD9945 SERIAL INTERFACE A0 SDATA A1 tDS A3 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 tDH SCK tLS tLH SL NOTES 1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE. 3. ALL 12 DATA BITS D0 TO D11 MUST BE WRITTEN. IF THE REGISTER CONTAINS FEWER THAN 12 BITS, ZEROS SHOULD BE USED FOR THE UNDEFINED BITS. Figure 4.
PAGE 10
AD9945 DC RESTORE INTERNAL VREF 6dB TO 40dB 0.1␮F CCDIN 2V FULL SCALE VGA CDS 12 12-BIT ADC CLPOB OPTICAL BLACK CLAMP 8-BIT DAC 10 DOUT DIGITAL FILTERING VGA GAIN REGISTER 8 CLAMP LEVEL REGISTER Figure 6. CCD Mode Block Diagram CIRCUIT DESCRIPTION AND OPERATION The AD9945 signal processing chain is shown in Figure 6. Each processing step is essential in achieving a high quality image from the raw CCD pixel data.
PAGE 11
AD9945 CCD MODE TIMING CCD SIGNAL N tID N+1 N+2 N+9 N+10 tID SHP tS1 tS2 tCP SHD DATACLK tOD OUTPUT DATA N–10 N– 9 N– 8 N– 1 N NOTES 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. Figure 8.
PAGE 12
AD9945 APPLICATIONS INFORMATION The AD9945 is a complete analog front end (AFE) product for digital still camera and camcorder applications. As shown in Figure 10, the CCD image (pixel) data is buffered and sent to the AD9945 analog input through a series input capacitor. The AD9945 performs the dc restoration, CDS, gain adjustment, black level correction, and analog-to-digital conversion. The AD9945’s digital output data is then processed by the image processing ASIC.
PAGE 13
AD9945 Internal Power-On Reset Circuitry After power-on, the AD9945 will automatically reset all internal registers and perform internal calibration procedures. This takes approximately 1 ms to complete. During this time, normal clock signals and serial write operations may occur. However, serial register writes will be ignored until the internal reset operation is completed. provide the lowest possible impedance path between the power and bypass pins and their respective ground pins.
PAGE 14
AD9945 OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 9 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 0.30 0.25 0.18 Figure 12.