2-Bit CCD Signal Processor with Precision Timing Core AD9949 FEATURES GENERAL DESCRIPTION New AD9949A supports CCD line length > 4096 pixels Correlated double sampler (CDS) 0 dB to 18 dB pixel gain amplifier (PxGA®) 6 dB to 42 dB 10-bit variable gain amplifier (VGA) 12-bit, 36 MSPS analog-to-digital converter (ADC) Black level clamp with variable level control Complete on-chip timing driver Precision Timing™ core with < 600 ps resolution On-chip 3 V horizontal and RG drivers 40-lead LFCSP package The AD
AD9949 TABLE OF CONTENTS Specifications..................................................................................... 3 Individual HBLK Sequences..................................................... 21 General Specifications ................................................................. 3 Generating Special HBLK Patterns .............................................. 23 Digital Specifications ................................................................... 3 Horizontal Sequence Control ...
AD9949 SPECIFICATIONS GENERAL SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE POWER SUPPLY VOLTAGE AVDD, TCVDD (AFE, Timing Core) HVDD (H1 to H4 Drivers) RGVDD (RG Driver) DRVDD (D0 to D11 Drivers) DVDD (All Other Digital) POWER DISSIPATION 36 MHz, HVDD = RGVDD = 3 V, 100 pF H1 to H4 Loading1 Total Shutdown Mode 1 Min Typ −20 −65 36 2.7 2.7 2.7 2.7 2.7 3.0 3.0 3.0 3.0 3.0 Max Unit +85 +150 °C °C MHz 3.6 3.6 3.6 3.6 3.
AD9949 ANALOG SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 36 MHz, typical timing specifications, unless otherwise noted. Table 3.
AD9949 TIMING SPECIFICATIONS CL = 20 pF, fCLI = 36 MHz, unless otherwise noted. Table 4.
AD9949 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD and TCVDD HVDD and RGVDD DVDD and DRVDD Any VSS Digital Outputs CLPOB/PBLK and HBLK SCK, SL, and SDATA RG H1 to H4 REFT, REFB, and CCDIN Junction Temperature Lead Temperature (10 s) With Respect to AVSS HVSS, RGVSS DVSS, DRVSS Any VSS DRVSS DVSS DVSS RGVSS HVSS AVSS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
AD9949 40 D0 (LSB) 39 CLP/PBLK 38 HBLK 37 DVDD 36 DVSS 35 HD 34 VD 33 SCK 32 SDI 31 SL PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9949 TOP VIEW 30 REFB 29 REFT 28 AVSS 27 CCDIN 26 AVDD 25 CLI 24 TCVDD 23 TCVSS 22 RGVDD 21 RG 03751-003 PIN 1 INDICATOR D9 11 D10 12 (MSB) D11 13 H1 14 H2 15 HVSS 16 HVDD 17 H3 18 H4 19 RGVSS 20 D1 1 D2 2 D3 3 D4 4 DRVSS 5 DRVDD 6 D5 7 D6 8 D7 9 D8 10 Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No.
AD9949 TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. Integral Nonlinearity (INL) INL is the deviation of each individual code measured from a true straight line from zero to full scale.
AD9949 EQUIVALENT INPUT/OUTPUT CIRCUITS AVDD DVDD R DVSS Figure 3. CCDIN (Pin 27) 03751-007 AVSS AVSS 03751-004 330Ω Figure 6. Digital Inputs (Pins 31 to 35, 38) AVDD HVDD OR RGVDD CLI 330Ω 25kΩ DATA + 03751-005 1.4V AVSS ENABLE DOUT DVSS DRVDD HVSS OR RGVSS DATA Figure 7. H1 to H4 and RG (Pins 14 to 15, 18 to 19, 21) DOUT DVSS DRVSS 03751-006 THREE-STATE Figure 5. Data Outputs D0 to D11 (Pins 1 to 4, 7 to 13, 40) Rev. B | Page 9 of 36 03751-008 Figure 4.
AD9949 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 400 350 0 –1.0 0 500 1000 1500 2000 2500 3000 ADC OUTPUT CODE 3500 4000 03751-009 –0.5 32 24 16 8 0 800 1000 03751-010 OUTPUT NOISE (LSB) 40 400 600 VGA GAIN CODE (LSB) VDD = 3.0V 250 VDD = 2.7V 200 24 30 SAMPLE RATE (MHz) Figure 10. Power Curves 48 200 VDD = 3.3V 150 18 Figure 8. Typical DNL 0 300 Figure 9. Output Noise vs. VGA Gain Rev. B | Page 10 of 36 36 03751-011 POWER DISSIPATION (mW) DNL (LSB) 0.
AD9949 SYSTEM OVERVIEW H-COUNTER BEHAVIOR V-DRIVER V1 TO Vx, VSG1 TO VSGx, SUBCK When the maximum horizontal count of 4096 pixels is exceeded, the H-counter in the AD9949 rolls over to zero and continues counting. It is, therefore, recommended that the maximum counter value not be exceeded. DOUT CCDIN CCD AD9949 INTEGRATED AFE + TD HD, VD DIGITAL IMAGE PROCESSING ASIC 03751-012 CLI SERIAL INTERFACE Figure 11. Typical Application However, the newer AD9949A version behaves differently.
AD9949 SERIAL INTERFACE TIMING The AD9949’s internal registers are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both the 8-bit address and 24-bit data-word are written starting with the LSB. To write to each register, a 32-bit operation is required, as shown in Figure 14. Although many registers are less than 24 bits wide, all 24 bits must be written for each register.
AD9949 COMPLETE REGISTER LISTING 1. 2. Table 7. SL Updated Registers All addresses and default values are expressed in hexadecimal. All registers are VD/HD updated as shown in Figure 14, except for the registers indicated in Table 7, which are SL updated. Register OPRMODE CTLMODE SW_RESET TGCORE _RSTB PREVENTUPDATE VDHDEDGE FIELDVAL HBLKRETIME CLPBLKOUT CLPBLKEN H1CONTROL RGCONTROL DRVCONTROL SAMPCONTROL DOUTPHASE Rev.
AD9949 Table 8. AFE Register Map Address 00 01 02 03 04 05 Data Bit Content [11:0] [9:0] [7:0] [11:0] [17:0] [17:0] Default Value 4 0 80 4 0 0 Name OPRMODE VGAGAIN CLAMP LEVEL CTLMODE PxGA GAIN01 PxGA GAIN23 Description AFE Operation Modes. (See Table 14.) VGA Gain. Optical Black Clamp Level. AFE Control Modes. (See Table 15.) PxGA Gain Registers for Color 0 [8:0] and Color 1 [17:9]. PxGA Gain Registers for Color 2 [8:0] and Color 3 [17:9]. Description Software Reset.
AD9949 Table 10. CLPOB Register Map Address 20 21 22 23 24 Data Bit Content [3:0] [23:0] [23:0] [23:0] [23:0] 25 26 27 28 [7:0] [11:0] [11:0] [11:0] Default Value (Hex) F FFFFFF FFFFFF FFFFFF FFFFFF 0 0 FFF FFF FFF Name CLPOBPOL CLPOBTOG_0 CLPOBTOG_1 CLPOBTOG_2 CLPOBTOG_3 CLPOBSCP0 CLPOBSPTR CLPOBSCP1 CLPOBSCP2 CLPOBSCP3 Description Start Polarities for CLPOB Sequences 0, 1, 2, and 3. Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 1.
AD9949 Table 12.
AD9949 Table 14. AFE Operation Register Detail Address 00 Data Bit Content [1:0] Default Value 0 Name PWRDOWN [2] 1 CLPENABLE [3] 0 CLPSPEED [4] 0 FASTUPDATE [5] 0 PBLK_LVL [7:6] [8] 0 0 TEST MODE DCBYP [9] [11:10] 0 0 TESTMODE CDSGAIN Description 0 = Normal Operation. 1 = Reference Standby. 2/3 = Total Power-Down 0 = Disable OB Clamp. 1 = Enable OB Clamp. 0 = Select Normal OB Clamp Settling. 1 = Select Fast OB Clamp Settling. 0 = Ignore VGA Update.
AD9949 PRECISION TIMING HIGH SPEED TIMING GENERATION The AD9949 generates flexible high speed timing signals using the Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE: the reset gate (RG), horizontal drivers (H1 to H4), and the SHP/SHD sample clocks. A unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling.
AD9949 Table 16. H1CONTROL, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters Parameter Polarity Positive Edge Negative Edge Sample Location Drive Control DOUT Phase Length 1b 6b 6b 6b 3b 6b Range High/Low 0 to 47 Edge Location 0 to 47 Edge Location 0 to 47 Sample Location 0 to 7 Current Steps 0 to 47 Edge Location Description Polarity Control for H1/H3 and RG (0 = No Inversion, 1 = Inversion). Positive Edge Location for H1/H3 and RG. Negative Edge Location for H1/H3 and RG.
AD9949 P[0] P[12] P[24] P[48] = P[0] P[36] CLI 1 PIXEL PERIOD tOD NOTES 1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. 2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS. 03751-020 DOUT Figure 19.
AD9949 HORIZONTAL CLAMPING AND BLANKING The AD9949’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual sequences are defined for each signal, which are then organized into multiple regions during image readout. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate different image transfer timing and high speed line shifts.
AD9949 ... HD ... HBL K H1/H3 THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1). ... H2/H4 03751-024 H1/H3 ... Figure 23. HBLK Masking Control TOG1 TOG2 TOG3 TOG4 TOG5 TOG6 HBLK H1/H3 SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS. 03751-025 H2/H4 Figure 24. Generating Special HBLK Patterns Table 20.
AD9949 GENERATING SPECIAL HBLK PATTERNS Six toggle positions are available for HBLK. Normally, only two of the toggle positions are used to generate the standard HBLK interval. However, the additional toggle positions may be used to generate special HBLK patterns, as shown in Figure 24. The pattern in this example uses all six toggle positions to generate two extra groups of pulses during the HBLK interval. By changing the toggle positions, different patterns can be created.
AD9949 H-COUNTER SYNCHRONIZATION The H-Counter reset occurs seven CLI cycles following the HD falling edge. The PxGA steering is synchronized with the reset of the internal H-Counter (see Figure 26). As mentioned in the H-Counter Behavior section, the AD9949 H-counter rolls over to zero and continues counting when the maximum counter length is exceeded. The newer AD9949A product does not roll over but holds at its maximum value until the next HD rising edge occurs.
AD9949 POWER-UP PROCEDURE RECOMMENDED POWER-UP SEQUENCE When the AD9949 is powered up, the following sequence is recommended (refer to Figure 27 for each step): 5. 1. 2. 3. 6. VDD (INPUT) CLI (INPUT) 7. 8. 9. 1 2 tPWR 3 4 5 6 7 8 SERIAL WRITES ... VD (OUTPUT) 9 1V ... ODD FIELD 2 1H ... EVEN FIELD ... HD (OUTPUT) H2/H4 DIGITAL OUTPUTS H1/H3, RG CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS UPDATED AT VD/HD EDGE Figure 27. Recommended Power-Up Sequence Rev.
AD9949 ANALOG FRONT END DESCRIPTION AND OPERATION Table 22. Adjustable CDS Gain The AD9949 signal processing chain is shown in Figure 28. Each processing step is essential in achieving a high quality image from the raw CCD pixel data. Operation Register Bits D11 D10 0 0 0 1 1 0 1 1 DC RESTORE To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 µF series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.
AD9949 VD HD SHP/SHD COLOR STEERING CONTROL 3 PxGA STEERING MODE SELECTION A third type of readout uses the Bayer pattern divided into three different readout fields. The 3-field mode should be used with this type of CCD (see Figure 32). The color steering performs the proper multiplexing of the R, G, and B gain values (loaded into the PxGA gain registers) and is synchronized by the user with vertical (VD) and horizontal (HD) sync pulses. For timing information, see Figure 35.
AD9949 FIELDVAL FIELDVAL = 0 FIELDVAL = 0 VD HD PxGA GAIN X REGISTER X 0 1 0 1 2 3 2 3 0 1 0 1 0 1 0 1 2 3 2 3 0 1 0 1 0 0 1 0 1 3 2 3 03751-034 NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE. 2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN 0101 AND 2323 LINES. 3. FIELDVAL IS ALWAYS RESET TO 0 ON VD FALLING EDGES. Figure 33.
AD9949 18 42 36 30 VGA GAIN (dB) The PxGA gain for each of the four channels is variable from 0 dB to 18 dB in 512 steps, specified using the PxGA GAIN01 and PxGA GAIN23 registers. The PxGA gain curve is shown in Figure 36. The PxGA GAIN01 register contains nine bits each for PxGA Gain0 and Gain1, and the PxGA GAIN23 register contains nine bits each for PxGA Gain2 and Gain3. 24 18 15 12 0 0 9 6 255 383 511 639 767 VGA GAIN REGISTER CODE 895 1023 Figure 37.
AD9949 APPLICATIONS INFORMATION CIRCUIT CONFIGURATION GROUNDING AND DECOUPLING RECOMMENDATIONS The AD9949 recommended circuit configuration is shown in Figure 38. Achieving good image quality from the AD9949 requires careful attention to PCB layout. All signals should be routed to maintain low noise performance. The CCD output signal should be directly routed to Pin 27 through a 0.1 µF capacitor.
AD9949 DRIVING THE CLI INPUT The AD9949’s master clock input (CLI) may be used in two different configurations, depending on the application. Figure 41 shows a typical dc-coupled input from the master clock source. When the dc-coupled technique is used, the master clock signal should be at standard 3 V CMOS logic levels. As shown in Figure 42, a 1000 pF ac-coupling capacitor may be used between the clock source and the CLI input.
AD9949 SEQUENCE 2 (OPTIONAL) 2 VERTICAL OB LINES V USE SEQUENCE 3 EFFECTIVE IMAGE AREA 10 VERTICAL OB LINES USE SEQUENCE 2 H 48 OB PIXELS 4 OB PIXELS 03751-044 HORIZONTAL CCD REGISTER 28 DUMMY PIXELS Figure 43. Example CCD Configuration SEQUENCE 1: VERTICAL BLANKING CCDIN INVALID PIX VERTICAL SHIFT DUMMY INVALID PIXELS VERT SHIFT SHP SHD H1/H3 H2/H4 HBLK 03751-045 PBLK CLPOB Figure 44.
AD9949 SEQUENCE 3: EFFECTIVE PIXEL LINES OPTICAL BLACK CCDIN OB VERTICAL SHIFT DUMMY EFFECTIVE PIXELS OPTICAL BLACK VERT SHIFT SHP SHD H1/H3 H2/H4 HBLK PBLK 03751-047 CLPOB Figure 46. Horizontal Sequences During Effective Pixels Rev.
AD9949 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX PIN 1 INDICATOR 0.50 BSC 5.75 BCS SQ TOP VIEW 0.50 0.40 0.30 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 31 30 40 1 4.25 4.10 SQ 3.95 EXPOSED PAD (BOTTO M VIEW) 10 11 21 20 0.25 MIN 4.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 47.
AD9949 NOTES Rev.
AD9949 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03751–0–11/04(B) Rev.
