400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer AD9951 FEATURES PLL REFCLK multiplier (4× to 20×) Internal oscillator, can be driven by a single crystal Phase modulation capability Multichip synchronization 400 MSPS internal clock speed Integrated 14-bit DAC 32-bit tuning word Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output) Excellent dynamic performance >80 dB SFDR @ 160 MHz (±100 kHz offset) AOUT Serial I/O control 1.
AD9951 TABLE OF CONTENTS Features .............................................................................................. 1 Component Blocks ..................................................................... 12 Applications ....................................................................................... 1 Modes of Operation ................................................................... 17 Revision History .............................................................................
AD9951 GENERAL DESCRIPTION The AD9951 is a direct digital synthesizer (DDS) featuring a 14-bit DAC operating up to 400 MSPS. The AD9951 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 MHz. The AD9951 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word).
AD9951 AD9951—ELECTRICAL SPECIFICATIONS Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, RSET = 3.92 kΩ, External Reference Clock Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.
AD9951 Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width Low Minimum Clock Pulse Width High Maximum Clock Rise/Fall Time Minimum Data Setup Time DVDD_I/O = 3.3 V Minimum Data Setup Time DVDD_I/O = 1.8 V Minimum Data Hold Time Maximum Data Valid Time Wake-Up Time2 Minimum Reset Pulse Width High I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.
AD9951 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Rating 150°C 4V 2V –0.7 V to +5.25 V –0.7 V to +2.
AD9951 DGND DGND OSK SYNC_CLK SYNC_IN DVDD_I/O DGND SDIO SCLK CS SDO IOSYNC PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 1 36 RESET DVDD 2 35 PWRDWNCTL DGND 3 34 DVDD AVDD 4 33 DGND AGND 5 32 AGND AVDD 6 31 AGND AGND 7 30 AGND OSC/REFCLK 8 29 AVDD OSC/REFCLK 9 28 AGND CRYSTAL OUT 10 27 AVDD CLKMODESELECT 11 26 AGND LOOP_FILTER 12 25 AVDD AD9951 16 17 18 19 20 21 22 23 24 AVDD AVDD AVDD IOUT IOUT AGND DACBP DAC_R S
AD9951 PIN FUNCTION DESCRIPTIONS Table 3. Pin Function Descriptions—48-Lead TQFP/EP Pin No. 1 Mnemonic I/O UPDATE I/O I 2, 34 3, 33, 42, 47, 48 4, 6, 13, 16, 18, 19, 25, 27, 29 5, 7, 14, 15, 17, 22, 26, 28, 30, 31, 32 8 DVDD DGND I I Description The rising edge transfers the contents of the internal buffer memory to the I/O registers. This pin must be set up and held around the SYNC_CLK output signal. Digital Power Supply Pins (1.8 V). Digital Power Ground Pins. AVDD I Analog Power Supply Pins (1.
AD9951 TYPICAL PERFORMANCE CHARACTERISTICS MKR1 98.0MHz –70.68dB ATTEN 10dB REF 0dBm 0 PEAK LOG –10 10dB/ –20 –20 –30 –30 MARKER 100.000000MHz –70.68dB –40 –50 –50 W1 S2 S3 FC –70 AA –80 –60 W1 S2 S3 FC –70 AA –80 1 –90 –100 VBW 3kHz SPAN 200MHz SWEEP 55.56 s (401 PTS) 03359-016 –90 –100 CENTER 100MHz #RES BW 3kHz REF 0dBm 0 PEAK LOG 10dB/ –10 –20 –20 –30 –30 MARKER 80.000000MHz –69.12dB –40 –50 –50 1 –90 1R 1 SPAN 200MHz SWEEP 55.
AD9951 ATTEN 10dB 1 MKR1 1.105MHz –5.679dBm REF –4dBm 0 PEAK LOG –10 10dB/ –20 –20 –30 –30 MARKER 1.105000MHz –5.679dBm –40 –50 –40 –50 W1 S2 S3 FC –70 AA –80 –60 W1 S2 S3 FC –70 AA –80 –90 ST –100 –90 ST –100 CENTER 1.105MHz #RES BW 30Hz VBW 30Hz SPAN 2MHz SWEEP 199.2 s (401 PTS) 03359-022 –60 REF 0dBm 0 PEAK LOG –10 10dB/ REF –4dBm 0 PEAK LOG –10 10dB/ 1R –20 –20 –30 –30 MARKER 40.000000MHz –56.2dB –40 –50 –40 –50 ATTEN 10dB 1 MKR1 120.205MHz –6.825dBm MARKER 120.
–20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M –120 –130 –140 –150 –160 –170 10 Figure 16. Residual Phase Noise with FOUT = 159.5 MHz, FCLK = 400 MSPS (Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue) 100 1k 10k FREQUENCY (Hz) 100k 1M 03359-029 0 –10 L(f) (dBc/Hz) 0 –10 03359-028 L(f) (dBc/Hz) AD9951 Figure 17. Residual Phase Noise with FOUT = 9.
AD9951 THEORY OF OPERATION COMPONENT BLOCKS DDS Core Clock Input The output frequency (fO) of the DDS is a function of the frequency of the system clock (SYSCLK), the value of the frequency tuning word (FTW), and the capacity of the accumulator (232, in this case). The exact relationship is given below with fS defined as the frequency of SYSCLK. The AD9951 supports various clock methodologies.
AD9951 DAC Output The AD9951 incorporates an integrated 14-bit current output DAC. Unlike most DACs, this output is referenced to AVDD, not AGND. Two complementary outputs provide a combined full-scale output current (IOUT). Differential outputs reduce the amount of common-mode noise that might be present at the DAC output, offering the advantage of an increased signal-to-noise ratio.
AD9951 Table 5. Register Map Register Name (Serial Address) Control Function Register No.1 (CFR1) (0x00) Control Function Register No.
AD9951 Control Register Bit Descriptions Control Function Register No. 1 (CFR1) CFR1<31:27>: Not Used CFR1<22> = 1. The software controlled manual synchronization feature is executed. The SYNC_CLK rising edge is advanced by one SYNC_CLK cycle and this bit is cleared. To advance the rising edge multiple times, this bit needs to be set for each advance. See the Synchronizing Multiple AD9951s section for details. CFR1<26>: Amplitude Ramp Rate Load Control Bit CFR1<21:14>: Not Used CFR1<26> = 0 (default).
AD9951 CFR1<6>: Not Used CFR1<5>: DAC Power-Down Bit CFR1<5> = 0 (default). The DAC is enabled for operation. CFR1<5> = 1. The DAC is disabled and is in its lowest power dissipation state. CFR2<11> = 1. The high speed sync enhancement is on. This bit should be set when attempting to use the auto-synchronization feature for SYNC_CLK inputs beyond 50 MHz, (200 MSPS SYSCLK). See the Synchronizing Multiple AD9951s section for details.
AD9951 Other Register Descriptions Amplitude Scale Factor (ASF) The ASF register stores the 2-bit auto ramp rate speed value and the 14-bit amplitude scale factor used in the output shaped keying (OSK) operation. In auto OSK operation, ASF <15:14> tells the OSK block how many amplitude steps to take for each increment or decrement. ASF<13:0> sets the maximum value achievable by the OSK internal multiplier. In manual OSK mode, ASF<15:14> has no effect. ASF <13:0> provide the output scale factor directly.
AD9951 AUTO Shaped On-Off Keying Mode Operation OSK Ramp Rate Timer The auto shaped on-off keying mode is active when CFR1<25> and CFR1<24> are set. When auto shaped on-off keying mode is enabled, a single scale factor is internally generated and applied to the multiplier input for scaling the output of the DDS core block (see Figure 18). The scale factor is the output of a 14-bit counter that increments/decrements at a rate determined by the contents of the 8-bit output ramp rate register.
AD9951 External Shaped On-Off Keying Mode Operation coupled with SYNC_CLK is used to transfer internal buffer contents into the control registers of the device. The combination of the SYNC_CLK and I/O UPDATE pins provides the user with constant latency relative to SYSCLK, and also ensures phase continuity of the analog output signal when a new tuning word or phase offset value is asserted. Figure 19 demonstrates an I/O UPDATE timing cycle and synchronization.
AD9951 SYSCLK A B A B SYNC_CLK I/O UPDATE DATA IN REGISTERS DATA 1 DATA 2 DATA 3 DATA 0 DATA 1 THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B. DATA 2 03359-007 DATA IN I/O BUFFERS Figure 20. I/O Synchronization Timing Diagram Synchronizing Multiple AD9951s The AD9951 product allows easy synchronization of multiple AD9951s.
AD9951 during Phase 2 of the communication cycle is a function of the register being accessed. For example, when accessing the Control Function Register No. 2, which is three bytes wide, Phase 2 requires that three bytes be transferred. If accessing the frequency tuning word, which is four bytes wide, Phase 2 requires that four bytes be transferred. After transferring all data bytes per the instruction, the communication cycle is completed. There are two phases to a communication cycle with the AD9951.
AD9951 INSTRUCTION BYTE The instruction byte contains the following information: Table 7. MSB R/Wb D6 X D5 X D4 A4 D3 A3 D2 A2 D1 A1 LSB A0 R/Wb—Bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. Logic High indicates read operation. Logic 0 indicates a write operation. serial port is in LSB first format. The instruction byte must be written in the format indicated by Control Register 0x00 <8>.
AD9951 When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is high, the AD9951 is put into a fast recovery power-down mode. In this mode, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry is NOT powered down. Table 8 indicates the logic level for each power-down bit that drives out of the AD9951 core logic to the analog section and the digital clock generation section of the chip for the external power-down operation.
AD9951 SUGGESTED APPLICATION CIRCUITS FREQUENCY TUNING WORD PHASE OFFSET WORD 1 I/I-BAR BASEBAND MODULATED/ DEMODULATED SIGNAL RF/IF INPUT 03359-012 REFCLK LPF AD9951 REFCLK CRYSTAL AD9951 DDS IOUT LPF REFCLK CRYSTAL OUT Figure 25. Synchronized LO for Upconversion/Down Conversion IOUT SYNC OUT RF OUT SYNC IN AD9951 DDS LOOP FILTER FREQUENCY TUNING WORD AD9951 TUNING WORLD IOUT LPF Figure 26. Digitally Programmable Divide-by-N Function in PLL Rev.
AD9951 OUTLINE DIMENSIONS 9.00 BSC SQ 1.20 MAX BOTTOM VIEW (PINS UP) 37 36 48 1 37 36 48 1 7.00 BSC SQ PIN 1 3.50 SQ TOP VIEW (PINS DOWN) 0° MIN 1.05 1.00 0.95 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY EXPOSED PAD 12 13 VIEW A 25 24 25 24 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 12 13 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
AD9951 NOTES Rev.
AD9951 NOTES Rev.
AD9951 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03359-0-5/09(A) Rev.
