Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9952YSVZ

400 MSPS 14-Bit, 1.8 V CMOS

Direct Digital Synthesizer

AD9952

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

400 MSPS internal clock speed

Integrated 14-bit DAC

32-bit tuning word

Phase noise ≤ −120 dBc/Hz @ 1 kHz offset (DAC output)

Excellent dynamic performance

>80 dB SFDR @ 160 MHz (±100 kHz offset) A

OUT

Serial I/O control

1.8 V power supply

Software and hardware controlled power-down

48-lead TQFP_EP package

Support for 5 V input levels on most digital inputs

PLL REFCLK multiplier (4× to 20×)

Internal oscillator, can be driven by a single crystal

Phase modulation capability

Multichip synchronization

High speed comparator (200 MHz toggle rate)

APPLICATIONS

Agile LO frequency synthesis

Programmable clock generators

Test and measurement equipment

Acousto-optic device drivers

GENERAL DESCRIPTION

The AD9952 is a direct digital synthesizer (DDS) featuring a

14-bit DAC (digital-to-analog converter) and operating up to

400 MSPS. The AD9952 uses advanced DDS technology,

coupled with an internal high speed, high performance DAC to

form a digitally programmable, complete high frequency

synthesizer capable of generating a frequency-agile analog

output sinusoidal waveform at up to 200 MHz. The AD9952 is

designed to provide fast frequency hopping and fine tuning

resolution (32-bit frequency tuning word). The frequency

tuning and control words are loaded into the AD9952 via a

serial I/O port.

The AD9952 is specified to operate over the extended industrial

temperature range of −40°C to +105°C.

FUNCTIONAL BLOCK DIAGRAM

COS(X)

CONTROL REGISTERS

OSCILLATOR/BUFFER

SYNC

ENABLE

I/O UPDATE

DAC_R

SET

DDS CORE

PHASE

OFFSET

PHASE

ACCUMULATOR

–1

IOUT

OSK

PWRDWNCTL

REFCLK

CRYSTAL OUT I/O PORT

DDS CLOCK

FREQUENCY

TUNING WORD

CLEAR PHASE

ACCUMULATOR

AMPLITUDE

SCALE FACTOR

DAC

SYSTEM

CLOCK

SYSTEM

CLOCK

SYNC_IN

SYNC_CLK

RESET

TIMING AND CONTROL LOGIC

TO 20

CLOCK

MULTIPLIER

÷ 4

AD9952

19 14

COMPARATOR

COMP_OUT

COMP_IN

03358-001

Figure 1.

Summary of content (28 pages)

PAGE 1
400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer AD9952 FEATURES APPLICATIONS 400 MSPS internal clock speed Integrated 14-bit DAC 32-bit tuning word Phase noise ≤ −120 dBc/Hz @ 1 kHz offset (DAC output) Excellent dynamic performance >80 dB SFDR @ 160 MHz (±100 kHz offset) AOUT Serial I/O control 1.
PAGE 2
AD9952 TABLE OF CONTENTS Features .............................................................................................. 1 Control Register Bit Descriptions ............................................ 16 Applications ....................................................................................... 1 Other Register Descriptions ..................................................... 18 General Description .........................................................................
PAGE 3
AD9952 ELECTRICAL SPECIFICATIONS AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, DAC_RSET = 3.92 kΩ, external reference clock frequency = 400 MHz with REFCLK multiplier disabled, unless otherwise noted. DAC output must be referenced to AVDD, not AGND. Table 1.
PAGE 4
AD9952 Parameter COMPARATOR INPUT CHARACTERISTICS Input Capacitance Input Resistance Input Current Hysteresis COMPARATOR OUTPUT CHARACTERISTICS Logic 1 Voltage, High Z Load Logic 0 Voltage, High Z Load Propagation Delay Output Duty Cycle Error Rise/Fall Time, 5 pF Load Toggle Rate, High Z Load Output Jitter2 COMPARATOR NARROW-BAND SFDR 10 MHz (±1 MHz) 10 MHz (±250 kHz) 10 MHz (±50 kHz) 10 MHz (±10 kHz) 70 MHz (±1 MHz) 70 MHz (±250 kHz) 70 MHz (±50 kHz) 70 MHz (±10 kHz) 110 MHz (±1 MHz) 110 MHz (±250 kHz) 11
PAGE 5
AD9952 Parameter Wake-Up Time6 Minimum Reset Pulse Width High I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V I/O UPDATE, SYNC_CLK Hold Time Latency I/O UPDATE to Frequency Change Propagation Delay I/O UPDATE to Phase Offset Change Propagation Delay I/O UPDATE to Amplitude Change Propagation Delay CMOS LOGIC INPUTS Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.
PAGE 6
AD9952 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Input Voltage (DVDD_I/O = 1.8 V) Digital Output Current Storage Temperature Range Operating Temperature Range Lead Temperature (10 sec Soldering) θJA θJC Rating 150°C 4V 2V –0.7 V to +5.25 V –0.7 V to +2.
PAGE 7
AD9952 SDO IOSYNC 44 CS SYNC_IN 45 SCLK SYNC_CLK 46 SDIO OSK 47 DVDD_I/O DGND 48 DGND DGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 43 42 41 40 39 38 37 I/O UPDATE 1 36 RESET DVDD 2 35 PWRDWNCTL DGND 3 34 DVDD AVDD 4 33 DGND AGND 5 32 AGND AVDD 6 AD9952 AGND 7 TOP VIEW (Not to Scale) REFCLK 8 REFCLK 9 31 COMP_IN 30 COMP_IN 29 AVDD 16 17 18 19 20 21 22 23 24 IOUT IOUT AGND DACBP DAC_RSET 15 AVDD 14 AVDD 13 AVDD 25 AVDD AGND LOOP_FILT
PAGE 8
AD9952 Pin No. 23 24 Mnemonic DACBP DAC_RSET I/O I I 28 30 31 35 36 COMP_OUT COMP_IN COMP_IN PWRDWNCTL RESET O I I I I 37 IOSYNC I 38 SDO O 39 40 41 CS SCLK SDIO I I I/O 43 44 DVDD_I/O SYNC_IN I I 45 46 SYNC_CLK OSK O I Paddle Exposed Paddle I Description DAC Biasline Decoupling Pin. A 0.1 μF capacitor to AGND is recommended. A resistor (3.92 kΩ nominal) connected from AGND to DAC_RSET establishes the reference current for the DAC. Comparator Output. Comparator Input.
PAGE 9
AD9952 TYPICAL PERFORMANCE CHARACTERISTICS MKR1 98.0MHz –70.68dB ATTEN 10dB REF 0dBm 0 PEAK LOG –10 10dB/ –20 –20 –30 –30 MARKER 100.000000MHz –70.68dB –40 –50 –50 –60 W1 S2 S3 FC –70 AA –80 –60 1 –90 –100 VBW 3kHz SPAN 200MHz SWEEP 55.56 s (401 PTS) 03358-003 –90 –100 CENTER 100MHz #RES BW 3kHz REF 0dBm 0 PEAK LOG –10 10dB/ –20 –20 –30 –30 MARKER 80.000000MHz –69.12dB –40 –50 –50 1 –90 1R 1 SPAN 200MHz SWEEP 55.56 s (401 PTS) –100 CENTER 100MHz #RES BW 3kHz Figure 4.
PAGE 10
AD9952 ATTEN 10dB 1 MKR1 1.105MHz –5.679dBm REF –4dBm 0 PEAK LOG –10 10dB/ –20 –20 –30 –30 MARKER 1.105000MHz –5.679dBm –40 –50 –40 –50 –60 –60 W1 S2 S3 FC –70 AA –80 –90 ST –100 –90 ST –100 CENTER 1.105MHz #RES BW 30Hz VBW 30Hz SPAN 2MHz SWEEP 199.2 s (401 PTS) 03358-009 W1 S2 S3 FC –70 AA –80 REF 0dBm 0 PEAK LOG –10 10dB/ REF –4dBm 0 PEAK LOG –10 10dB/ 1R –20 –20 –30 –30 MARKER 40.000000MHz –56.2dB –40 –50 –40 –50 ATTEN 10dB 1 MKR1 120.205MHz –6.825dBm MARKER 120.
PAGE 11
AD9953 Figure 16. Residual Phase Noise with FOUT = 159.5 MHz, FCLK = 400 MSPS (Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue) Figure 18. Residual Phase Noise with FOUT = 9.5 MHz, FCLK = 400 MSPS (Green), 4 ×100 MSPS (Red), and 20 × 20 MSPS (Blue) t1 = 3.156ns t2 = 3.04ns t = –116.0PS 1/t = –8.621GHz FALL (R1) = 396.4PS RISE(R2) = 464.3PS R1 R2 CH1 200mV M 200PS 20.0GS/S A CH1 708mV 03374-0-030 03374-0-031 1 IT 4.0PS/PT 3.1ns REF2 200mV 500ns Figure 17.
PAGE 12
AD9952 EQUIVALENT INPUT/OUTPUT CIRCUITS COMPARATOR INPUTS DIGITAL INPUTS DVDD_I/O INPUT COMP_IN 03358-021 COMP_IN Figure 21. Comparator Inputs 03358-019 AVOID OVERDRIVING DIGITAL INPUTS. FORWARD-BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS. COMPARATOR OUTPUT Figure 19. Digital Inputs AVDD DIGITAL OUTPUTS IOUT 03358-022 IOUT MUST TERMINATE OUTPUTS TO AVDD FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. 03358-020 Figure 22. Comparator Outputs Figure 20.
PAGE 13
AD9952 THEORY OF OPERATION COMPONENT BLOCKS Clock Input DDS Core The AD9952 supports various clock methodologies. Support for differential or single-ended input clocks and enabling of an onchip oscillator and/or a PLL multiplier is all controlled via userprogrammable bits. The AD9952 can be configured in one of six operating modes to generate the system clock. The modes are configured using the CLKMODESELECT pin, Control Function Register 1 (CFR1) [4], and CFR2 [7:3].
PAGE 14
AD9952 Table 4. Clock Input Modes of Operation CFR1 [4] Low Low Low Low High CLKMODESELECT High High Low Low X CFR2 [7:3] 3 < M < 21 M < 4 or M > 20 3 < M < 21 M < 4 or M > 20 X Oscillator Enabled Yes Yes No No No System Clock FCLK = FOSC × M FCLK = FOSC FCLK = FOSC × M FCLK = FOSC FCLK = 0 Frequency Range (MHz) 80 < FCLK < 400 20 < FCLK < 30 80 < FCLK < 400 10 < FCLK < 400 N/A DAC Output Comparator The AD9952 incorporates an integrated 14-bit current output DAC.
PAGE 15
AD9952 Table 5. Register Map Register Name (Serial Address) Control Function Register 1 (CFR1) Register Address (0x00) Bit Range [7:0] (MSB) Bit 7 Digital PowerDown Bit 6 Comparator PowerDown Bit 5 DAC PowerDown [15:8] Not Used Not Used Auto Clr Phase Accum.
PAGE 16
AD9952 The CFR1 bits control the functions, features, and modes of the AD9952. The functionality of each bit is detailed below. CFR1 [22] = 1. The software controlled manual synchronization feature is executed. The SYNC_CLK rising edge is advanced by one SYNC_CLK cycle and this bit is cleared. To advance the rising edge multiple times, this bit needs to be set for each advance (see the Synchronizing Multiple AD9952 section).
PAGE 17
AD9952 CFR1 [6]: Comparator Power-Down Bit CFR1 [6] = 0 (default). The comparator is enabled for operation. CFR1 [6] = 1. The comparator is disabled and is in its lowest power dissipation state. CFR2 [11] = 1. The high speed sync enhancement is on. This bit should be set when using the autosynchronization feature for SYNC_CLK inputs beyond 50 MHz, (200 MSPS SYSCLK). See the Synchronizing Multiple AD9952S section.
PAGE 18
AD9952 OTHER REGISTER DESCRIPTIONS PROGRAMMING FEATURES Amplitude Scale Factor (ASF) Phase Offset Control The ASF register stores the 2-bit auto ramp rate speed value and the 14-bit amplitude scale factor used in the output shaped keying (OSK) operation. In auto OSK operation, ASF [15:14] tell the OSK block how many amplitude steps to take for each increment or decrement. ASF [13:0] sets the maximum value for the OSK internal multiplier. In manual OSK mode, ASF [15:14] have no effect.
PAGE 19
AD9952 The shaped on-off keying function can be bypassed (disabled) by clearing the OSK enable bit (CFR1 [25] = 0). The modes are controlled by two bits located in the most significant byte of the control function register (CFR). CFR1 [25] is the shaped on-off keying enable bit. When CFR1 [25] is set, the output scaling function is enabled and CFR1 [25] bypasses the function. CFR1 [24] is the internal shaped on-off keying active bit.
PAGE 20
AD9952 External Shaped On-Off Keying Mode Operation The external shaped on-off keying mode is enabled by writing CFR1 [25] to a Logic 1 and writing CFR1 [24] to a Logic 0. When configured for external shaped on-off keying, the content of the ASFR becomes the scale factor for the data path. The scale factors are synchronized to SYNC_CLK via the I/O UPDATE functionality. SYNCHRONIZING MULTIPLE AD9952s The AD9952 product allows easy synchronization of multiple AD9952s.
PAGE 21
AD9952 Instruction Byte Details The instruction byte contains the following information. (MSB) D7 R/W D6 X D5 X D4 A5 D3 A4 D2 A3 D1 A2 (LSB) D0 A1 R/W—Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. Logic High indicates a read operation; a Logic 0 indicates a write operation. X, X—Bit 6 and Bit 5, respectively, of the instruction byte are don’t care. SYNC_CLK I/O UPDATE TSU DVDD I/O = 3.3V 1.
PAGE 22
AD9952 SYSCLK A B A B SYNC_CLK I/O UPDATE DATA IN REGISTERS DATA 1 DATA 2 DATA 3 DATA 0 DATA 1 DATA 2 03358-031 DATA IN I/O BUFFERS THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B. Figure 26. Timing of I/O Update Signal vs. Actual Register Update Serial Interface Port Pin Description ●●● SCLK ●●● ●●● SDIO TCSU TDSU TDH DVDD I/O = 3.3V DVDD I/O = 1.
PAGE 23
AD9952 When in LSB-first mode, the device reads the instruction byte first (LSB to MSB), then calculates the expected number of bytes from the address provided, and then receives/provides data from the referenced register in LSB-first format (LSB to MSB of the register selected). Example Operation In this example, the amplitude scale factor is calculated and written to present a 45° phase offset on the output of the AD9952. First, the default MSB-first case is considered.
PAGE 24
AD9952 Table 7. Power-Down Control Functions Control PWRDWNCTL = 0 CFR1 [3] don’t care Mode Active Software control PWRDWNCTL = 1 CFR1 [3] = 0 External control, fast recovery power-down mode PWRDWNCTL = 1 CFR1 [3] = 1 External control, full power-down mode Rev.
PAGE 25
AD9952 LAYOUT CONSIDERATIONS For the best performance, the following layout guidelines should be observed. Always provide the analog power supply (AVDD) and the digital power supply (DVDD) on separate supplies, even if just from two different voltage regulators driven by a common supply.
PAGE 26
AD9952 SUGGESTED APPLICATION CIRCUITS MODULATED/ DEMODULATED SIGNAL 03358-027 RF/IF INPUT LPF AD9952 REFCLK Figure 29. Synchronized LO for Upconversion/Down Conversion PHASE COMPARATOR LOOP FILTER VCO AD9952 FILTER 03358-028 REF SIGNAL TUNING WORD Figure 30. Digitally Programmable Divide-by-N Function in PLL TUNING WORD IOUT LPF IOUT LPF AD9952 DDS AD9952 03358-029 ON-CHIP COMPARATOR CMOS LEVEL CLOCK Figure 31.
PAGE 27
AD9952 OUTLINE DIMENSIONS 9.00 BSC SQ 1.20 MAX BOTTOM VIEW (PINS UP) 37 36 48 1 37 36 48 1 7.00 BSC SQ PIN 1 3.50 SQ TOP VIEW (PINS DOWN) 0° MIN 1.05 1.00 0.95 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY EXPOSED PAD 12 13 VIEW A 25 24 25 24 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 12 13 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.