Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9956YCPZ

2.7 GHz DDS-Based

Agile

Synthesizer

AD9956

Rev. A

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infringements of patents or other rights of third parties that may result from its use.

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Tel: 781.329.4700

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FEATURES

400 MSPS internal DDS clock speed

48-bit frequency tuning word

14-bit programmable phase offset

Integrated 14-bit DAC

Excellent dynamic performance

Phase noise ≤ 135 dBc/Hz @ 1 KHz offset

−80 dB SFDR @ 160 MHz (±100 KHz offset I

OUT

)

25 Mb/s write-speed serial I/O control

200 MHz phase frequency detector inputs

655 MHz programmable input dividers for the phase

frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)

Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)

8 phase/frequency profiles

1.8 V supply for device operation

3.3 V supply for I/O and charge pump

Software controlled power-down

48-lead LFCSP package

Automatic linear frequency sweeping capability (in DDS)

Programmable charge pump current (up to 4 mA)

Phase modulation capability

Multichip synchronization

Dual-mode PLL lock detect

655 MHz CML-mode PECL-compliant driver

APPLICATIONS

Agile LO frequency synthesis

FM chirp source for radar and scanning systems

Automotive radars

Test and measurement equipment

Acousto-optic device drivers

FUNCTIONAL BLOCK DIAGRAM

FREQUENCY

ACCUMULATOR

PHASE

ACCUMULATOR

PHASE

OFFSET

PHASE

OFFSET

WORD

TIMING AND CONTROL LOGIC

PHASE TO

AMPLITUDE

CONVERSION

FTW

DAC

RF-DIVIDER

÷R

FROM PLLOSC

PS<2:0>

RESET I/O PORT

CHARGE

PUMP

SCALER

ΦBUFFER

BUFFER

CP_OUT

CP_RSET

PLL_LOCK/SYNC_IN

I/O_UPDATE

SYNC_OUT

REFCLK

CML CLOCK DRIVER

DRV DRV DRV_RSET

DAC_RSET

IOUT

SYNC_CLK

SYSCLK

DELTA

FREQUENCY

TUNING WORD

DELTA

FREQUENCY

RAMP RATE

SYSCLK

LOCK

DETECT

19 14

DDS CORE

SYSCLK

I/O_RESET

OSCILLATOR

CHARGE

PUMP

PLLREF/

PLLREF

PLLOSC/

PLLOSC

÷N

÷4

÷M

04806-0-001

Figure 1.

Summary of content (32 pages)

PAGE 1
2.7 GHz DDS-Based AgileRFTM Synthesizer AD9956 3.
PAGE 2
AD9956 TABLE OF CONTENTS Product Overview............................................................................. 3 CML Driver................................................................................. 19 Specifications..................................................................................... 4 Modes of Operation ....................................................................... 20 Loop Measurement Conditions..................................................
PAGE 3
AD9956 PRODUCT OVERVIEW The AD9956 is Analog Devices’ newest AgileRF synthesizer. The device is comprised of DDS and PLL circuitry. The DDS features a 14-bit DAC operating at up to 400 MSPS and a 48-bit frequency tuning word (FTW). The PLL circuitry includes a phase frequency detector with scaleable 200 MHz inputs (divider inputs operate up to 655 MHz) and digital control over the charge pump current. The device also includes a 655 MHz CML-mode PECL-compliant driver with programmable slew rates.
PAGE 4
AD9956 SPECIFICATIONS AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ TA = 25°C) DAC_RSET = 3.92 kΩ, CP_RSET = 3.09 kΩ, DRV_RSET = 4.02 kΩ, unless otherwise noted. Table 1.
PAGE 5
AD9956 Parameter LOGIC INPUTS (SDI/O, I/O_RESET, RESET, I/O_UPDATE, PS0 to PS2, SYNC_IN) VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL Input Current CIN, Maximum Input Capacitance LOGIC OUTPUTS (SDO, SYNC_OUT, PLL_LOCK)6 VOH, Output High Voltage VOH, Output Low Voltage IOH IOL POWER CONSUMPTION Total Power Consumed, All Functions On IAVDD IDVDD IDVDD_I/O ICP_VDD Power-Down Mode WAKE-UP TIME (from Power-Down Mode) Digital Power-Down (CFR1<7>) DAC Power-Down (CFR2<39>) RF Divider Power-Down (CFR2<
PAGE 6
AD9956 Parameter 160 MHz Analog Out (±1 MHz) 160 MHz Analog Out (±250 kHz) 160 MHz Analog Out (±50 kHz) DAC Residual Phase Noise 19.7 MHz FOUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset 51.84 MHz FOUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset 105.3 MHz Analog Out @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset 155.
PAGE 7
AD9956 Parameter Latencies/Pipeline Delays7 I/O Update to DAC Frequency Change I/O Update to DAC Phase Change PS<2:0> to DAC Frequency Change PS<2:0> to DAC Phase Change I/O Update to CP_OUT Scaler Change I/O Update to Frequency Accumulator Step Size Change I/O Update to Frequency Accumulator Ramp Rate Change RF DIVIDER/CML DRIVER EQUIVALENT INTRINSIC TIME JITTER FIN = 414.72 MHz, FOUT = 51.84 MHz BW = 12 kHz −> 400 kHz FIN = 1244.16 MHz, FOUT = 155.52 MHz BW = 12 kHz −> 1.3 MHz FIN = 2488.
PAGE 8
AD9956 Parameter TOTAL SYSTEM JITTER AND PHASE NOISE FOR 105.33 MHz ADC CLOCK GENERATION CIRCUIT Converter Limiting Jitter Resultant SNR Phase Noise of Fundamental @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ ≥1 MHz Offset Min Typ Max Unit 0.53 67 ps rms dB −75 −87 −93 −105 −145 −152 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 1 Test Conditions/Comments See the Loop Measurement Conditions section The input impedance of the REFCLK input is 1500 Ω.
PAGE 9
AD9956 LOOP MEASUREMENT CONDITIONS 622 MHz OC-12 Clock 105 MHz Converter Clock VCO = Sirenza 190-640T VCO = Sirenza 190-845T Reference = Wenzel 500-10116 (30.3 MHz) Reference = Wenzel 500-10116 (30.3 MHz) Loop Filter = 10 kHz BW, 60° Phase Margin Loop Filter = 10 kHz BW, 45° Phase Margin C1 = 170 nF, R1 = 14.4 Ω, C2 = 5.11 µF, R2 = 89.3 Ω, C3 Omitted C1 = 117 nF, R1 = 28 Ω, C2 = 1.6 µF, R2 = 57.1 Ω, C3 = 53.
PAGE 10
AD9956 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD_I/0) Charge Pump Supply Voltage (CPVDD) Maximum Digital Input Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Thermal Resistance (θJA) Rating 2V 2V 3.6 V 3.6 V −0.5 V to DVDD_I/O + 0.
PAGE 11
AD9956 48 47 46 45 44 43 42 41 40 39 38 37 AVDD DAC_RSET DRV_RSET CP_RSET AVDD AGND PLLOSC PLLOSC PLLREF PLLREF AVDD AGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND 3 AVDD 4 IOUT 5 IOUT 6 AVDD 7 AGND 8 I/O_RESET 9 RESET 10 DVDD 11 DGND 12 AD9956 TOP VIEW (Not to Scale) SDO SDI/O SCLK CS DVDD_I/O SYNC_OUT PLL_LOCK/SYNC_IN I/O_UPDATE PS0 PS1 PS2 DGND NC = NO CONNECT PIN 1 INDICATOR 36 35 34 33 CP_OUT CP_VDD AGND DRV 32 31 30 29 28 27 26 25 DRV CP_VDD AGND REFCLK REFCLK AVDD AGND DVDD 04806-
PAGE 12
AD9956 Table 3. 48-Lead LFCSP Pin Function Description Pin No. 1, 3, 8, 26, 30, 34, 37, 43, 49 2, 4, 7, 27, 38, 44, 48 5 6 9 Mnemonic AGND Description Analog Ground. AVDD Analog Core Supply (1.8 V). IOUT IOUT I/O_RESET DAC Analog Output. DAC Analog Complementary Output. Resets the serial port when synchronization is lost in communications but does not reset the device itself (ACTIVE HIGH). When not being used, this pin should be forced low, because it floats to the threshold value. Master RESET.
PAGE 13
AD9956 TYPICAL PERFORMANCE CHARACTERISTICS REF LVL 0dBm RBW 500Hz VBW 500Hz 20s SWT DELTA 1 [T1] –84.82dB –404.80961924kHz 0 RF ATT 20dB UNIT 0 1 A –10 –10 –20 –20 –30 –30 –40 RBW 10kHz VBW 10kHz 4.3s SWT DELTA 1 [T1] –67.45dB 74.50901804MHz REF LVL 0dBm dB RF ATT 20dB UNIT dB 1 A –40 1 AP 1 AP –50 –50 –60 –60 –70 –70 –80 1 –100 CENTER 10.1MHz 100kHz/ –90 –100 SPAN 1MHz START 0Hz Figure 4.
PAGE 14
AD9956 REF LVL 0dBm RBW 500kHz VBW 500kHz 20s SWT DELTA 1 [T1] –78.13dB –100.20040080kHz RF ATT 20dB UNIT REF LVL 0dBm dB 0 DELTA 1 [T1] –56.33dB –80.96192385MHz RBW 10kHz VBW 10kHz 5s SWT RF ATT 20dB UNIT dB 0 1 1 A –10 –10 –20 –20 –30 –30 –40 A –40 1 AP 1 AP –50 –50 –60 –60 –70 –70 –80 04806-0-021 CENTER 159.
PAGE 15
10k 100k FREQUENCY (Hz) 1M 10M L(f) (dBc/Hz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M L(f) (dBc/Hz) 100 1k 10k 100k FREQUENCY (Hz) 1M 10k 100k FREQUENCY (Hz) 1M 10M 100M 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 20. Total System Phase Noise for 105 MHz Converter Clock 04806-0-029 L(f) (dBc/Hz) Figure 17.
PAGE 16
AD9956 TYPICAL APPLICATION CIRCUITS 25MHz CRYSTAL PHASE FREQUENCY DETECTOR/CHARGE PUMP ÷M PLLREF ÷N PLLOSC 400MHz CP_OUT VCO LPF CML DRIVER ÷R DAC DDS CLOCK1′ LPF Figure 22. Dual-Clock Configuration PLLREF CP_OUT PLLOSC ÷R DDS 04806-0-011 DAC VCO LPF LPF AD9956 Figure 23. Fractional-Divider Loop CML DRIVER DDS 8-LEVEL FSK (FC = 100MHz) DAC BPF ÷R AD9956 BPF PLLREF CP_OUT ÷N PLLOSC VCO 2.5GHz TONE LPF Figure 24. LO and Baseband Modulation Generation Rev.
PAGE 17
AD9956 EXTERNAL REFERENCE PHASE FREQUENCY DETECTOR ÷M ÷N REF 622MHz CHARGE PUMP OSC VCO LPF CML DRIVER ÷R AD9956 DAC DDS CLOCK2 04806-0-013 CLOCK1 Figure 25. Optical Networking Clock PHASE FREQUENCY DETECTOR DDS DAC PLLREF LPF ÷N CHARGE PUMP VCO ≤650MHz LPF 04806-0-014 PLLOSC Figure 26. Direct Upconversion APPLICATION CIRCUIT EXPLANATIONS Dual-Clock Configuration In this loop, M = 1, N = 16, and R = 4.
PAGE 18
AD9956 GENERAL DESCRIPTION DDS CORE The DDS can create digital phase relationships by clocking a 48-bit accumulator. The incremental value loaded into the accumulator, known as the frequency tuning word, controls the overflow rate of the accumulator. Similar to a sine wave completing a 2π radian revolution, the overflow of the accumulator is cyclical in nature and generates a base frequency according to the following equation.
PAGE 19
AD9956 CML DRIVER • RF divider input • RF divider output • PLLOSC input RISING EDGE SURGE CONTINUOUS I(t) CONTINUOUS FALLING EDGE SURGE t ~250ps ~250ps Figure 27. Rising Edge and Falling Edge Surge Current Output of the CML Clock Driver, as Opposed to the Steady State Continuous Current Rev. A | Page 19 of 32 04806-0-002 For clocking applications, an on-chip current mode logic (CML) driver is included. This CML driver generates very low jitter clock edges.
PAGE 20
AD9956 MODES OF OPERATION DDS MODES OF OPERATION Single-Tone Mode This is the default mode of operation for the DDS core. The phase accumulator runs at a fixed frequency, as per the active profile’s tuning word. Likewise, any phase offset applied to the signal is a static value, which comes from the phase offset word of the active profile. The device has eight different phase/frequency profiles, each with its own 48-bit frequency tuning word and 14-bit phase offset word.
PAGE 21
AD9956 Automatic Synchronization Manual Synchronization, Software Controlled In automatic synchronization mode, the device is placed into slave mode and automatically aligns the internal SYNC_CLK to a master SYNC_CLK signal, supplied on the SYNC_IN input. When this bit is enabled, the PLL_LOCK is not available as an output, however, an out-of-lock condition can be detected by reading Control Function Register 1 and checking the status of the PLL_LOCK_ERROR bit, CFR1<24>.
PAGE 22
AD9956 SERIAL PORT OPERATION register being accessed. For example, when accessing Control Function Register 2, which is four bytes wide, Phase 2 requires that four bytes be transferred. If accessing a frequency tuning word, which is six bytes wide, Phase 2 requires that six bytes be transferred. After transferring all data bytes per the instruction, the communication cycle is completed. An AD9956 serial data-port communication cycle has two phases.
PAGE 23
AD9956 INSTRUCTION BYTE MSB/LSB TRANSFERS The instruction byte contains the following information: The AD9956 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSB first bit in Control Register 1 (CFR1<15>). The default value of this bit is low (MSB first). When CFR1 <15> is set high, the AD9956 serial port is in LSB first format.
PAGE 24
AD9956 REGISTER MAP AND DESCRIPTION Table 5. Register Name (Serial Address) Control Function Register 1 (CFR1) (0x00) Control Function Register 2 (CFR2) (0x01) Bit Range <31:24> (MSB) Bit 7 Open1 Bit 6 Open1 Bit 5 Open1 Bit 4 Open1 Bit 3 Open1 Bit 2 Open1 Bit 1 Open1 <23:16> LOAD SRR @ I/O_UPDATE Auto-Clr Frequency Accum. Enable Sine Output Clear Frequency Accum. Clear Phase Accum.
PAGE 25
AD9956 Register Name (Serial Address) Profile Control Register No. 0 (PCR0) (0x06) Profile Control Register No. 1 (PCR1) (0x07) Profile Control Register No. 2 (PCR2) (0x08) Profile Control Register No.
PAGE 26
AD9956 Register Name (Serial Address) Profile Control Register No. 4 (PCR4) (0x0A) Profile Control Register No. 5 (PCR5) (0x0B) Profile Control Register No. 6 (PCR6) (0x0C) Profile Control Register No.
PAGE 27
AD9956 CONTROL FUNCTION REGISTER DESCRIPTIONS Control Function Register 1 (CFR1) This control register is comprised of four bytes, all of which must be written during a write operation involving CFR1. CFR1 is used to control various functions, features, and operating modes of the AD9956. The functionality of each bit(s) is described below. In general, the bit is named for the function it serves when the bit is set. CFR1<31:25> Open. Unused locations.
PAGE 28
AD9956 CFR1<7> Digital Power-Down CFR1 <17> Linear Sweep Enable This bit turns on the frequency accumulator, which enables the DDS to perform linear sweeping. This bit powers down the digital circuitry not directly related to the I/O port. The I/O port functionality is not suspended, regardless of the state of this bit. CFR1<17> = 0 (default). The DDS generates frequencies in single-tone mode. CFR1<7> = 0 (default). Digital logic operating as normal. CFR1<17> = 1.
PAGE 29
AD9956 CFR1<3> = 0 (default). The automatic synchronization function of the DDS core is disabled. CFR1<3> = 1. The automatic synchronization function is on. The device is slaved to an external reference and adjusts the internal SYNC_CLK to match the external reference, which is supplied on the SYNC_IN input. CFR2<39> DAC Power-Down Bit This bit powers down the DAC portion of the AD9956 and puts it into the lowest power dissipation state. CFR2<39> = 0 (default). DAC is powered on and operating.
PAGE 30
AD9956 CFR2<28:26> Clock Driver Falling Edge Control These bits control the slew rate of the CML clock driver output’s falling edge. When these bits are on, additional current is sent to the output driver to increase the rising edge slew rate capability. Table 7 describes how the bits increase the current; the contributions of each bit are cumulative. Note that the additional current is on only during the rising edge of the waveform, for approximately 250 ps, but not on during the entire transition.
PAGE 31
AD9956 CFR2<15:12> PLLREF Divider Control Bits (÷N) These 4 bits set the PLLREF divider (÷N) ratio where N is a value equal to 1 to 16. CFR2<15:12> = 0000 means that N = 1 and CFR2<15:12> = 1111 means that N = 16, or simply, N = CFR2<15:12> + 1. CFR2<15:12> = 0000 0001 0010 0011 0100 0101 0110 0111 N= 1 2 3 4 5 6 7 8 CFR2<15:12> = 1000 1001 1010 1011 1100 1101 1110 1111 N= 9 10 11 12 13 14 15 16 CFR2<5> = 1. The charge pump is configured to operate with a ground referenced VCO.
PAGE 32
AD9956 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 1 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 12 13 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR 48 EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 35.