GSPS Quadrature Digital Upconverter with 18-Bit I/Q Data Path and 14-Bit DAC AD9957 Data Sheet FEATURES GENERAL DESCRIPTION 1 GSPS internal clock speed (up to 400 MHz analog output) Integrated 1 GSPS 14-bit DAC 250 MSPS input data rate Phase noise ≤ −125 dBc/Hz (400 MHz carrier @ 1 kHz offset) Excellent dynamic performance >80 dB narrow-band SFDR 8 programmable profiles for shift keying Sin(x)/(x) correction (inverse sinc filter) Reference clock multiplier Internal oscillator for a single crystal opera
AD9957 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RAM Control .................................................................................. 27 Applications ....................................................................................... 1 RAM Overview ........................................................................... 27 General Description ...................................................
Data Sheet AD9957 Sync Generator ............................................................................40 I/O_RESET—Input/Output Reset ........................................ 48 Sync Receiver ...............................................................................41 I/O_UPDATE—Input/Output Update ................................ 48 Setup/Hold Validation ................................................................42 Serial I/O Timing Diagrams .........................................
AD9957 Data Sheet REVISION HISTORY 4/12—Rev. B to Rev. C Changes to Table 1 ............................................................................ 7 Changes to Table 3 .......................................................................... 11 Change to Sync Generator Section............................................... 41 Changes to Sync Receiver Section and Setup/Hold Validation Section ..............................................................................................
Data Sheet AD9957 SPECIFICATIONS ELECTRICAL SPECIFICATIONS AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD (3.3V) = 3.3 V ± 5%, DVDD_I/O (3.3V) = 3.3 V ± 5%, T = 25°C, RSET = 10 kΩ, IOUT = 20 mA, external reference clock frequency = 1000 MHz with REFCLK multiplier disabled, unless otherwise noted. Table 1.
AD9957 Parameter NOISE SPECTRAL DENSITY (NSD) Single Tone fOUT = 20.1 MHz fOUT = 98.6 MHz fOUT = 201.1 MHz fOUT = 397.8 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fOUT = 25 MHz fOUT = 50 MHz fOUT = 100 MHz MODULATOR CHARACTERISTICS Input Data Error Vector Magnitude WCDMA—FDD (TM1), 3.
Data Sheet Parameter CMOS LOGIC INPUTS Voltage Logic 1 Logic 0 Current Logic 1 Logic 0 Input Capacitance XTAL_SEL INPUT Logic 1 Voltage Logic 0 Voltage Input Capacitance CMOS LOGIC OUTPUTS Voltage Logic 1 Logic 0 POWER SUPPLY CURRENT DVDD_I/O (3.3V) Pin Current Consumption DVDD (1.8V) Pin Current Consumption AVDD (3.3V) Pin Current Consumption AVDD (1.
AD9957 Data Sheet ABSOLUTE MAXIMUM RATINGS DIGITAL INPUTS Table 2. DVDD_I/O Rating 2V 4V −0.7 V to +4 V −0.7 V to +2.2 V 5 mA −65°C to +150°C −40°C to +85°C 22°C/W 2.8°C/W 150°C 300°C AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS. 06384-003 INPUT Figure 2. Equivalent Input Circuit DAC OUTPUTS AVDD Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Data Sheet AD9957 1 2 AGND NC NC AGND DAC_RSET AVDD (3.3V) AGND 87 86 85 84 83 82 AVDD (3.3V) AVDD (1.8V) 88 AVDD (3.3V) REF_CLK 89 76 REF_CLK 90 AGND AVDD (1.8V) 91 77 NC 92 AGND REFCLK_OUT 93 78 XTAL_SEL 94 79 AGND 95 IOUT NC 96 IOUT NC 97 80 NC 98 81 NC 99 PIN 1 INDICATOR 75 AVDD (3.3V) 74 AVDD (3.3V) AGND NC AVDD (1.8V) 3 73 AGND 4 72 AGND 5 71 AVDD (1.
AD9957 Data Sheet Table 3. Pin Function Descriptions Pin No. 1, 24, 61, 72, 86, 87, 93, 97 to 100 2 3, 6, 89, 92 74 to 77, 83 17, 23, 30, 47, 57, 64 11, 15, 21, 28, 45, 56, 66 4, 5, 73, 78, 79, 82, 85, 88, 96 13, 16, 22, 29, 46, 58, 62, 63, 65 7 Mnemonic NC I/O 1 Description Not Connected. Allow device pin to float. PLL_LOOP_FILTER AVDD (1.8V) AVDD (3.3V) DVDD (1.8V) I I I I PLL-Loop Filter Compensation. See External PLL Loop Filter Components section. Analog Core VDD. 1.8 V analog supplies.
Data Sheet AD9957 Pin No. 59 Mnemonic I/O_UPDATE I/O 1 I/O 60 OSK I 67 SDIO I/O 68 SDO O 69 SCLK I 70 CS I 71 I/O_RESET I 80 IOUT O 81 IOUT O 84 DAC_RSET O 90 91 REF_CLK REF_CLK I I 94 REFCLK_OUT O 95 XTAL_SEL I (EPAD) Exposed Pad (EPAD) 1 Description Input/Output Update; Digital Input Or Output (Active High) Depending on the Internal I/O Update Active Bit.
AD9957 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1 1 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 1 –70 –70 –80 –80 –90 START 0Hz 50MHz/DIV –90 –100 STOP 500MHz CENTER 102MHz 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 1 –70 –80 –80 06384-050 –70 –90 –100 START 0MHz 50MHz/DIV –100 STOP 500MHz CENTER 222MHz 5kHz/DIV SPAN 50kHz Figure 9.
AD9957 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 06384-044 0 START 0Hz 50MHz/DIV –100 STOP 500MHz Figure 11. QPSK, 7.8125 Msymbols/s, 4x Oversampled Raised Cosine, α = 0.
AD9957 Data Sheet –50 –90 fOUT = 397.8MHz –100 –55 –110 MAGNITUDE (dBc/Hz) SFDR (dBc) SFDR WITHOUT PLL –60 SFDR WITH PLL –65 fOUT = 201.1MHz –120 fOUT = 98.6MHz –130 –140 –150 –70 0 50 100 150 200 250 300 350 –170 10 400 100 06384-061 06384-058 100M fOUT = 397.8MHz –100 –50 MAGNITUDE (dBc/ Hz) HIGH SUPPLY –55 SFDR (dBc) 10M –90 LOW SUPPLY –60 –65 fOUT = 201.1MHz –110 –120 –130 –140 fOUT = 20.
Data Sheet AD9957 1200 –20 –30 DVDD 1.8V –40 800 –50 –60 600 –70 –80 400 –90 AVDD 1.8V 200 0 400 AVDD 3.3V –100 500 600 700 800 900 06384-064 DVDD 3.3V 06384-063 POWER DISSIPATION (mW) 1000 –110 CENTER 143.86MHz 1000 SYSTEM CLOCK FREQUENCY (MHz) Figure 23. Power Dissipation vs. System Clock (PLL Enabled) 2.55MHz/DIV SPAN 25.5MHz Tx CHANNEL BANDWIDTH: 3.84MHz W-CDMA SGFF FWD POWER: –11.88dBm ADJACENT CHANNEL BANDWIDTH: 3.84MHz SPACING: 3MHz LOWER: –78.27dB UPPER: –78.
AD9957 Data Sheet MODES OF OPERATION than that of the DAC. An internal chain of rate interpolation filters the user data and upsamples to the DAC sample rate. Combined, the filters provide for programmable rate interpolation while suppressing spectral images and retaining the original baseband spectrum. OVERVIEW The AD9957 has three basic operating modes. Quadrature modulation (QDUC) mode (default) Interpolating DAC mode Single tone mode QDUC mode employs both the DDS and the rate interpolation filters.
Data Sheet AD9957 The PROFILE and I/O_UPDATE pins are also synchronous to the PDCLK. QUADRATURE MODULATION MODE The DDS core provides a quadrature (sine and cosine) local oscillator signal to the quadrature modulator, where the interpolated I and Q samples are multiplied by the respective phase of the carrier and summed together, producing a quadrature modulated data stream. This data stream is routed through the inverse sinc filter (optionally), and the output scaling multiplier.
AD9957 Data Sheet The Blackfin interface includes an additional pair of half-band filters in both I and Q signal paths (not shown explicitly in the diagram). The two half-band filters increase the interpolation of the baseband data by a factor of four, relative to the normal QDUC mode. BLACKFIN INTERFACE (BFI) MODE The synchronization of the serial data occurs through the PDCLK signal. In BFI mode, the PDCLK signal is effectively the bit clock for the serial data.
Data Sheet AD9957 INTERPOLATING DAC MODE No modulation takes place in the interpolating DAC mode; therefore, the spectrum of the data supplied at the parallel port remains at baseband. However, a sample rate conversion takes place based on the programmed interpolation rate. The interpolation hardware processes the signal, effectively performing an oversample with a zero-stuffing operation.
AD9957 Data Sheet SINGLE TONE MODE cosine or sine output of the DDS. The sinusoid at the DDS output can be scaled using a 14-bit amplitude scale factor (ASF) and optionally routed through the inverse sinc filter. Single tone mode offers the output shift keying (OSK) function. It provides the ability to ramp the amplitude scale factor between zero and an arbitrary preset value over a programmable time interval.
Data Sheet AD9957 SIGNAL PROCESSING For a better understanding of the operation of the AD9957, it is helpful to follow the signal path in quadrature modulation mode from the parallel data port to the output of the DAC, examining the function of each block (see Figure 26). The internal system clock (SYSCLK) signal that generates from the timing source provided to the REF_CLK pins provides all timing within the AD9957.
AD9957 Data Sheet TxENABLE tDS PDCLK tDH tDS I1 I2 I3 IK – 1 IK 06384-010 I0 D<17:0> tDH Figure 30. 18-Bit Parallel Port Timing Diagram—Interpolating DAC Mode TxENABLE tDS PDCLK tDH tDS Q0 I1 Q1 IN QN 06384-011 I0 D<17:0> tDH Figure 31.
Data Sheet AD9957 INVERSE CCI FILTER The inverse cascaded comb integrator (CCI) filter predistorts the data, compensating for the slight attenuation gradient imposed by the CCI filter (see the Programmable Interpolating Filter section). Data entering the first half-band filter occupies a maximum bandwidth of ½ fIQ as defined by Nyquist (where fIQ is the sample rate at the input of the first half-band filter); see Figure 33.
AD9957 Data Sheet Knowledge of the frequency response of the half-band filters is essential to understanding their impact on the spectral properties of the input signal. This is especially true when using the quadrature modulator to upconvert a baseband signal containing complex data symbols that have been pulse shaped. Consider that a complex symbol is represented by a real (I) and an imaginary (Q) component, thus requiring two digital words to represent a single complex sample of the form I + jQ.
Data Sheet AD9957 QUADRATURE MODULATOR The digital quadrature modulator stage shifts the frequency of the baseband spectrum of the incoming data stream up to the desired carrier frequency (a process known as upconversion). At this point, the baseband data, which was delivered to the device at an I/Q sample rate of fIQ, has been upsampled to a rate equal to the frequency of SYSCLK, making the data sampling rate equal to the sampling rate of the carrier signal.
AD9957 Data Sheet In Figure 37, it can be seen that the sinc envelope introduces a frequency dependent attenuation that can be as much as 4 dB at the Nyquist frequency (half of the DAC sample rate). Without the inverse sinc filter, the DAC output also suffers from the frequency dependent droop of the sinc envelope. The inverse sinc filter effectively flattens the droop to within ±0.05 dB as shown in Figure 38, which shows the corrected sinc response with the inverse sinc filter enabled.
Data Sheet AD9957 RAM CONTROL RAM OVERVIEW The AD9957 has an integrated 1024 × 32-bit RAM. This RAM is only accessible when the AD9957 is operating in QDUC or interpolating DAC mode. The RAM has two fundamental modes of operation: data entry/retrieve mode and playback mode. The mode is selected by programming the RAM Enable bit in CFR1 via the serial I/O port. Data entry/retrieve mode is used to load or read back the RAM contents via the serial I/O port.
AD9957 Data Sheet LOAD/RETRIEVE RAM OPERATION Loading or retrieving the RAM contents is a three-step process. rate when the playback destination is the baseband scaling multipliers. Although RAM load/retrieve operations via the serial I/O port take precedence over playback, it is recommended that the user not attempt RAM access via the serial I/O port when the RAM enable bit is set. 1.
Data Sheet 3 16 10 10 AD9957 RAM MODE ADDRESS STEP RATE START ADDRESS END ADDRESS RT RAM Ramp-Up Mode SDIO SDO SCLK I/O_RESET CS In ramp-up mode, upon assertion of an I/O update or a state change on the RT pin, the RAM begins playback operation using the parameters programmed into the selected RAM segment register. Data is extracted from RAM over the specified address range contained in the start address and end address of the active RAM segment register.
AD9957 Data Sheet A Logic 1 to Logic 0 transition on the RT pin instructs the state machine to switch to RAM Segment Register 1 and to decrement through the address range starting with the end address. As long as the RT pin remains Logic 0, the state machine continues to play back the RAM data until it reaches the start address, at which point the state machine halts.
Data Sheet AD9957 The circled numbers in Figure 44 indicate specific events, explained as follows: Event 5—the RT pin switches to Logic 1. The state machine initializes to the start address of RAM Segment Register 0, resets the internal timer, and begins incrementing the RAM address counter. Event 1—an I/O update or profile change activates the RAM bidirectional ramp mode. Event 2—the RT pin switches to Logic 1.
AD9957 Data Sheet 1 PDCLK CYCLE OR M DDS CLOCK CYCLES Δt END ADDRESS RAM ADDRESS 1 Δt 1 3 2 06384-025 START ADDRESS I/O_UPDATE OR RT TRANSITION Figure 45. Continuous Bidirectional Ramp Timing Diagram RAM Continuous Bidirectional Ramp Mode In continuous bidirectional ramp mode, upon assertion of an I/O update or a state change on the RT pin, the RAM begins playback operation using the parameters programmed into the selected RAM segment register.
Data Sheet AD9957 1 PDCLK CYCLE OR M DDS CLOCK CYCLES Δt END ADDRESS RAM ADRESS 1 START ADDRESS 2 1 4 3 5 06384-026 I/O_UPDATE OR RT TRANSITION Figure 46. Continuous Recirculate Timing Diagram RAM Continuous Recirculate Mode The continuous recirculate mode mimics ramp-up mode, except that when the state machine reaches the end address of the active RAM segment register, it does not halt.
AD9957 Data Sheet CLOCK INPUT (REF_CLK) REFCLK OVERVIEW The AD9957 supports a number of options for producing the internal SYSCLK signal (that is, the DAC sample clock) via the REF_CLK/REF_CLK input pins. The REF_CLK input can be driven directly from a differential or single-ended source, or it can accept a crystal connected across the two input pins. There is also an internal phase-locked loop (PLL) multiplier that can be independently enabled.
Data Sheet AD9957 Figure 51 shows the boundaries of the VCO frequency ranges over the full range of temperature and supply voltage variation for an individual device selected from the population. Figure 51 shows that the VCO frequency ranges for a single device always overlap when operated over the full range of conditions. 0.1µF DIFFERENTIAL SOURCE, DIFFERENTIAL INPUT. 90 REF_CLK PECL, LVPECL, OR LVDS DRIVER TERMINATION 91 REF_CLK 0.1µF BALUN (1:1) SINGLE-ENDED SOURCE, DIFFERENTIAL INPUT.
AD9957 Data Sheet PLL CHARGE PUMP The charge pump current (ICP) is programmable to provide the user with additional flexibility to optimize the PLL performance. Table 8 lists the bit settings vs. the nominal charge pump current. Table 8. PLL Charge Pump Current ICP (CFR3<21:19>) 000 001 010 011 100 101 110 111 In the prevailing literature, this configuration yields a thirdorder, Type II PLL.
Data Sheet AD9957 ADDITIONAL FEATURES OUTPUT SHIFT KEYING (OSK) The OSK function (Figure 53) is only available in single tone mode. It allows the user to control the output signal amplitude of the DDS. Both manual and automatic modes are available.
AD9957 Data Sheet Table 9. OSK Amplitude Step Size I/O_UPDATE PIN ASF<1:0> 00 01 10 11 By default, the I/O_UPDATE pin is an input that serves as a strobe signal to allow synchronous update of the device operating parameters. For example, frequency, phase, and amplitude control words for the DDS can be programmed using the serial I/O port.
Data Sheet AD9957 POWER-DOWN CONTROL The AD9957 offers the ability to independently power down four specific sections of the device. Power-down functionality applies to the digital core, DAC, auxiliary DAC, and REFCLK input. A power-down of the digital core disables the ability to update the serial I/O port. However, the digital power-down bit can still be cleared via the serial port to prevent the possibility of a nonrecoverable state.
AD9957 Data Sheet SYNCHRONIZATION OF MULTIPLE DEVICES OVERVIEW The internal clocks of the AD9957 provide the timing for the propagation of data along the baseband signal processing path. These internal clocks are derived from the internal system clock (SYSCLK) and are all submultiples of the SYSCLK frequency. The logic state of all of these clocks in aggregate during any given SYSCLK cycle defines a unique clock state.
Data Sheet ÷16 D Q ÷2R 5 0 R 1 SYNC POLARITY 9 PROGAMMABLE DELAY SYNC_OUT 10 LVDS DRIVER SYNC GENERATOR DELAY SYNC GENERATOR ENABLE 06384-033 SYSCLK AD9957 Figure 56. Sync Generator The sync generator produces an LVDS-compatible clock signal with a 50% duty cycle that appears at the SYNC_OUT pins. The frequency of the SYNC_OUT signal can be one of two possible rates.
AD9957 Data Sheet CLOCK STATE SYNC STATE PRESET VALUE LVDS RECEIVER SYNC_IN+ 7 SYNC_IN– 8 SYNC_SMP_ERR 12 SYNC RECEIVER DELAY 5 PROGAMMABLE DELAY SYNC RECEIVER ENABLE RISING EDGE DETECTOR AND STROBE GENERATOR P R E S E T Q0 . . . . . . INTERNAL CLOCKS QN LOAD CLOCK GENERATOR SETUP AND HOLD VALIDATION SYNC TIMING VALIDATION DISABLE 6 SYSCLK 4 SYNC VALIDATION DELAY SYNC PULSE 06384-034 DELAYED SYNC-IN SIGNAL Figure 57.
Data Sheet AD9957 Because the programmed value of the sync validation delay establishes the time window for a setup/hold measurement, the amount of delay is an important consideration for proper operation of the validation block. The value chosen should represent a small fraction of the SYSCLK period. For example, if the SYSCLK frequency is 1 GHz (1000 ps period), then a reasonable sync validation delay value is 4 (~300 ps).
AD9957 Data Sheet SYNCHRONIZATION EXAMPLE To accomplish the synchronization of multiple devices provide each AD9957 with a SYNC_IN signal that is edge aligned across all the devices. If the SYNC_IN signal is edge aligned at all devices, and all devices have the same sync receiver delay and sync state preset value, then they all have matching clock states (that is, they are synchronized). Figure 59 shows this concept with three AD9957s in synchronization.
Data Sheet AD9957 I/Q PATH LATENCY The I/Q latency through the AD9957 is easiest to describe in terms of system clock (SYSCLK) cycles and is a function of the AD9957 configuration (that is, which mode and which optional features are engaged). The I/Q latency is primarily affected by the programmable CCI rate. The values in Table 12 should be considered estimates because observed latency may be data dependent. The latency was calculated using the linear delay model for FIR filters.
AD9957 Data Sheet POWER SUPPLY PARTITIONING The AD9957 features multiple power supplies, and their power consumption varies with its configuration. This section covers which power supplies can be grouped together and how the power consumption of each block varies with frequency. The values quoted in this section are for comparison only. Refer to Table 1 for exact values. With each group, bypass capacitors of 1 μF in parallel with a 10 μF capacitor should be used. 1.
Data Sheet AD9957 SERIAL PROGRAMMING CONTROL INTERFACE—SERIAL I/O The AD9957 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The interface allows read/write access to all registers that configure the AD9957. MSB-first or LSB-first transfer formats are supported.
AD9957 Data Sheet SDO—Serial Data Out SERIAL I/O TIMING DIAGRAMS Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9957 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Figure 60 through Figure 63 provide basic examples of the timing relationships between the various control signals of the serial I/O port.
Data Sheet AD9957 I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK RELATIONSHIPS The I/O_UPDATE pin is used to transfer data from the serial I/O buffer to the active registers in the device. Data in the buffer is inactive. SYNC_CLK is a rising edge active signal. It is derived from the system clock and a divide-by-4 frequency divider. SYNC_CLK, which is externally provided, can be used to synchronize external hardware to the AD9957 internal clocks. I/O_UPDATE initiates the start of a buffer transfer.
AD9957 Data Sheet REGISTER MAP AND BIT DESCRIPTIONS REGISTER MAP Note that the highest number found in the Bit Range column for each register in the following tables is the MSB and the lowest number is the LSB for that register. Table 13.
Data Sheet AD9957 Table 14.
AD9957 Data Sheet Table 15.
Data Sheet AD9957 Table 16.
AD9957 Data Sheet Table 17.
Data Sheet AD9957 REGISTER BIT DESCRIPTIONS The serial I/O port registers span an address range of 0 to 25 (0x00 to 0x19 in hexadecimal notation). This represents a total of 26 registers. However, six of these registers are unused, yielding a total of 20 available registers. The unused registers are 7, 8, 11 to 13, and 23 (0x07 to 0x08, 0x0B to 0x0D, and 0x17). The number of bytes assigned to the registers varies.
AD9957 Bit (s) 9 Mnemonic OSK (Output Shift Keying) Enable 8 Select Auto-OSK 7 Digital PowerDown 6 DAC Power-Down 5 REFCLK Input Power-Down 4 Auxiliary DAC Power-Down 3 External PowerDown Control 2 Auto Power-Down Enable 1 SDIO Input Only 0 LSB First Data Sheet Description 0: OSK disabled (default). 1: OSK enabled. Ineffective unless CFR1<9> = 1. 0: manual OSK enabled (default). 1: automatic OSK enabled. This bit is effective without the need for an I/O update.
Data Sheet Bit (s) 21:17 16 Mnemonic Open Read Effective FTW 15:14 I/O Update Rate Control 13 PDCLK Rate Control 12 Data Format 11 PDCLK Enable 10 PDCLK Invert 9 TxEnable Invert 8 Q-First Data Pairing 7 6 Open Data Assembler Hold Last Value 5 Sync Timing Validation Disable 4:0 Open AD9957 Description 0: a serial I/O port read operation of the FTW register reports the contents of the FTW register (default).
AD9957 Data Sheet Control Function Register 3 (CFR3) Address 0x02, four bytes are assigned to this register. Table 20. Bit Descriptions for CFR3 Register Bit (s) 31:30 29:28 27 26:24 23:22 21:19 18:16 15 Mnemonic Open DRV0 Open VCO SEL Open ICP Open REFCLK Input Divider Bypass 14 REFCLK Input Divider ResetB 13:9 8 Open PLL Enable 7:1 0 N Open Description Controls REFCLK_OUT pin (see Table 6 for details); default is 01b.
Data Sheet AD9957 RAM Segment Register 1 Address 0x06, six bytes are assigned to this register. This register is only active if CFR1<31> = 1 and there is a Logic 1 to Logic 0 transition on the RT pin. Table 24.
AD9957 Data Sheet PROFILE REGISTERS There are eight consecutive serial I/O addresses (0x0E to 0x15) dedicated to device profiles. All eight profile registers are either single tone profiles or QDUC profiles depending on the device operating mode specified by CFR1<25:24>. During operation, the active profile register is determined via the external PROFILE<2:0> pins. Single tone profiles control: DDS frequency (32 bits), DDS phase offset (16 bits), and DDS amplitude scaling (14 bits).
Data Sheet AD9957 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 76 100 1 75 76 75 100 1 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) 5.00 SQ 0° MIN 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 51 25 26 BOTTOM VIEW (PINS UP) 51 50 26 0.50 BSC LEAD PITCH VIEW A 25 50 0.27 0.22 0.
AD9957 Data Sheet NOTES Rev.
Data Sheet AD9957 NOTES Rev.
AD9957 Data Sheet NOTES ©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06384-0-4/12(C) Rev.
