Dual-Channel, 14-Bit, CCD Signal Processor with Precision Timing Core AD9974 FEATURES GENERAL DESCRIPTION 1.
AD9974 TABLE OF CONTENTS Features .............................................................................................. 1 Precision Timing High Speed Timing Core ............................. 15 Applications ....................................................................................... 1 Horizontal Clamping and Blanking ......................................... 18 General Description .........................................................................
AD9974 SPECIFICATIONS X = A = B, unless otherwise noted. Table 1. Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD_X (AFE, Timing Core) RGVDD_X (RG_X Driver) HVDD_X (H1_X to H4_X Drivers) DVDD_X (All Other Digital) DRVDD_X (Parallel Data Output Drivers) IOVDD_X (I/O Supply Without the Use of LDO) POWER SUPPLY CURRENTS—65 MHz OPERATION AVDD_X (1.8 V) RGVDD_X (3.3 V, 20 pF RG Load) HVDD_X 1 (3.3 V, 200 pF Total Load on H1 to H4) DVDD_X (1.8 V) DRVDD_X (3.0 V) IOVDD_X (1.
AD9974 TIMING SPECIFICATIONS X = A = B, CL = 20 pF, AVDD_X = DVDD_X = 1.8 V, fCLI = 65 MHz, unless otherwise noted. Table 3.
AD9974 DIGITAL SPECIFICATIONS X = A = B, IOVDD_X = 1.6 V to 3.6 V, RGVDD_X = HVDD_X = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted. Table 4.
AD9974 ANALOG SPECIFICATIONS X = A = B, AVDD_X = 1.8 V, fCLI = 65 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted. Table 5.
AD9974 MAXIMUM INPUT LIMIT = LESSER OF 2.2V OR (AVDD + 0.3V) +1.8V TYP (AVDD) 800mV MAXIMUM 200mV MAX OPTICAL BLACK PIXEL +1.3V TYP (AVDD – 0.5V) DC RESTORE VOLTAGE 1V MAXIMUM INPUT SIGNAL RANGE (0dB CDS GAIN) 0V (AVSS) MINIMUM INPUT LIMIT (AVSS – 0.3V) Figure 2. Input Signal Characteristics Rev.
AD9974 ABSOLUTE MAXIMUM RATINGS Ratings apply to both Channel A and Channel B, unless otherwise noted. Table 6. Parameter AVDD to AVSS DVDD to DVSS DRVDD to DRVSS IOVDD to DVSS HVDD to HVSS RGVDD to RGVSS Any VSS RG Output to RGVSS H1 to H4, HL Output to HVSS SCK, SL, SDI to DVSS REFT, REFB, CCDINM, CCDINP to AVSS Junction Temperature Lead Temperature (10 sec) Rating −0.3 V to +2.2 V −0.3 V to +2.2 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to RGVDD + 0.
AD9974 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9974 TOP VIEW (Not to Scale) A1 CORNER INDEX AREA 1 2 3 4 5 6 7 8 9 10 A B C D E F G H 05955-003 J K Figure 3. Pin Configuration Table 8.
AD9974 Ball Location D10 D9 B10 J8 K9 E9 E10 C9 C10 B9 Mnemonic H3_B H4_B RG_B DRVSS_B DRVDD_B HVSS_B HVDD_B RGVSS_B RGVDD_B IOVDD_B Type 1 DO DO DO P P P P P P P A10 B7 A8 F8 F7 E8 E7 A3 G1 H1 J1 K1 G2 H2 K2 G3 H3 J3 K4 J4 H4 G4 B5, C5, D5, E5, F5, G5, H5, J5, K5, B6, C6, D6, E6, F6, G6, H6, J6, K6 A9 G7 H7 J7 K7 G8 H8 K8 G9 H9 J9 K10 J10 H10 G10 LDO_OUT_B AVSS_B AVDD_B DVSS_B DVDD_B VD_B HD_B AVDD_A D0_A D1_A D2_A D3_A D4_A D5_A D6_A D7_A D8_A D9_A D10_A D11_A D12_A D13_A GND P P P P P DI DI P DO DO
AD9974 TYPICAL PERFORMANCE CHARACTERISTICS 10 250 8 200 6 TOTAL POWER LSB POWER (mW) 4 150 3.3V SUPPLIES 100 2 0 –2 –4 50 1.8V SUPPLIES 30 35 40 45 50 55 60 65 SAMPLE RATE (MHz) –8 0 2k 8k 10k 12k 14k 16k Figure 7. Integral Nonlinearity 180 1.0 160 0.8 140 0.6 120 INL MISMATCH (%) 100 80 60 40 0.4 0.2 0 –0.2 –0.4 –0.6 20 0 5 10 15 20 25 30 35 40 45 VGA GAIN (dB) 05955-006 –0.8 0 Figure 5. RMS Output Noise vs. VGA Gain 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.
AD9974 EQUIVALENT INPUT/OUTPUT CIRCUITS IOVDD AVDD 330Ω R CLI 100kΩ AVSS 05955-011 AVSS 05955-010 + AVSS Figure 11. CLI Input, Register 0x15[0] = 1 Enables the Bias Circuit Figure 9. CCDIN Input HVDD OR RGVDD DATA IOVDD OUTPUT ENABLE HVSS OR RGVSS Figure 10. Digital Inputs Figure 12. H1 to H4 and RG Outputs Rev.
AD9974 TERMINOLOGY MAX Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore, every code must have a finite width. No missing codes guaranteed to 14-bit resolution indicates that all 16,384 codes, each for its respective input, must be present over all operating conditions. Total Output Noise The rms output noise is measured using histogram techniques.
AD9974 THEORY OF OPERATION All AD9974 clocks are synchronized with VD and HD inputs. All of the AD9974 horizontal pulses (CLPOB, PBLK, and HBLK) are programmed and generated internally. V DRIVER V1 > Vx, VSG1 > VSGx, SUBCK H1_A TO H4_A, RG_A H1_B TO H4_B, RG_B The H-drivers for H1 to H4 and RG are included in the AD9974, allowing these clocks to be directly connected to the CCD. An H-driver voltage of 3 V is supported in the AD9974.
AD9974 PROGRAMMABLE TIMING GENERATION Using a 65 MHz CLI frequency, the edge resolution of the Precision Timing core is approximately 240 ps. If a 1× system clock is not available, it is possible to use a 2× reference clock by programming the CLIDIVIDE register (Address 0x0D). The AD9974 then internally divides the CLI frequency by 2. PRECISION TIMING HIGH SPEED TIMING CORE The AD9974 generates flexible high speed timing signals using the Precision Timing core.
AD9974 1 2 H1, H3 4 3 H2, H4 05955-019 H1 TO H4 PROGRAMMABLE LOCATIONS: 1H1 RISING EDGE. 2H1 FALLING EDGE. 3H2 RISING EDGE. 4H2 FALLING EDGE. Figure 19. HCLK Mode 2 Operation 1 2 H1 H2 3 4 H3 H4 05955-020 H1 TO H4 PROGRAMMABLE LOCATIONS: 1H1 RISING EDGE. 2H1 FALLING EDGE. 3H3 RISING EDGE. 4H3 FALLING EDGE. Figure 20.
AD9974 Table 9. HCLK Modes, Selected by HCLKMODE Register (Address 0x23[7:5]) HCLK Mode Mode 1 Mode 2 Register Value 001 010 Mode 3 100 Invalid Selection 000, 011, 101, 110, 111 Description H1 edges are programmable, with H3 = H1 and H2 = H4 = inverse of H1. H1 edges are programmable, with H3 = H1. H2 edges are programmable, with H4 = H2. H1 edges are programmable, with H2 = inverse of H1. H3 edges are programmable, with H4 = inverse of H3. Invalid register settings. Table 10.
AD9974 HORIZONTAL CLAMPING AND BLANKING CLPOB and PBLK Masking Area The horizontal clamping and blanking pulses of the AD9974 are fully programmable to suit a variety of applications. Individual control is provided for CLPOB, PBLK, and HBLK during the different regions of each field. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate different image transfer timing and high speed line shifts.
AD9974 Table 11.
AD9974 Individual HBLK Patterns HBLK Mode 0 Operation The HBLK programmable timing shown in Figure 25 is similar to CLPOB and PBLK; however, there is no start polarity control. Only the toggle positions designate the start and the stop positions of the blanking period. Additionally, as shown in Figure 26, there is a polarity control, HBLKMASK, for H1/H3 and H2/H4 that designates the polarity of the horizontal clock signals during the blanking period.
AD9974 Register HBLKTOGO1 HBLKTOGO2 HBLKTOGO3 HBLKTOGO4 HBLKTOGO5 HBLKTOGO6 HBLKTOGE1 HBLKTOGE2 HBLKTOGE3 HBLKTOGE4 HBLKTOGE5 HBLKTOGE6 RA0H1REPA/B/C Length (Bits) 13 13 13 13 13 13 13 13 13 13 13 13 12 Range 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0
AD9974 HBLK Mode 1 Operation Increasing H-Clock Width During HBLK Enable multiple repeats of the HBLK signal by setting HBLK_MODE to 1. In this mode, the HBLK pattern can be generated using a different set of registers: HBLKSTART, HBLKEND, HBLKLEN, and HBLKREP, along with the six toggle positions (see Figure 28). HBLK Mode 0 and HBLK Mode 1 allow the H1 to H4 pulse width to be increased during the HBLK interval.
AD9974 Figure 31 shows the following example: HBLK Mode 2 Operation RA0H1REPA/RA0H1REPB/RA0H1REPC = RA0H2REPA/RA0H2REPB/RA0H2REPC = RA1H1REPA/RA1H1REPB/RA1H1REPC = RA1H2REPA/RA1H2REPB/RA1H2REPC = 2. HBLK Mode 2 allows more advanced HBLK pattern operation. If unevenly spaced HCLK pulses in multiple areas are needed, HBLK Mode 2 can be used. Using a separate set of registers, HBLK Mode 2 can divide the HBLK region into up to six repeat areas (see Table 12).
AD9974 For example, if the desired toggle position is 100, CLPOB_TOG should be set to 88 (that is, 100 − 12). Figure 49 shows the 12-cycle pipeline delay referenced to the falling edge of HD. HBLK, PBLK, and CLPOB Toggle Positions The AD9974 uses an internal horizontal pixel counter to position the HBLK, PBLK, and CLPOB toggle positions. The horizontal counter does not reset to 0 until 12 CLI periods after the falling edge of HD.
AD9974 COMPLETE FIELD—COMBINING H-PATTERNS H-Pattern Selection After the H-patterns are created, they combine to create different readout fields. A field consists of up to nine different regions determined by the SCP registers. Within each region, a different H-pattern group can be selected up to a maximum of 32 groups. Registers to control the H-patterns are located in the field registers. Table 31 describes the field registers. The H-patterns are stored in the HPAT memory, as described in Table 20.
AD9974 MODE REGISTERS The mode registers contain registers to select the final field timing of the AD9974. Typically, all of the field and H-pattern group information is programmed into the AD9974 at startup. During operation, the mode registers allow the user to select any combination of field timing to meet the current requirements of the system.
AD9974 H-PATTERN MEMORY FIELD 0 FIELD 1 FIELD 2 FIELD 3 EXAMPLE 1: TOTAL FIELDS = 3, FIRST FIELD = FIELD 0, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 2 FIELD_SEL1 = 0 FIELD 0 FIELD_SEL2 = 1 FIELD 1 FIELD_SEL3 = 2 FIELD 2 EXAMPLE 2: TOTAL FIELDS = 1, FIRST FIELD = FIELD 3 FIELD_SEL1 = 3 FIELD 3 EXAMPLE 3: TOTAL FIELDS = 4, FIRST FIELD = FIELD 5, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 4, FOURTH FIELD = FIELD 2 FIELD 5 FIELD_SEL2 = 1 FIELD 1 FIELD_SEL3 = 4 FIELD 4 FIELD_SEL4 = 2 FIELD 2 05
AD9974 Figure 36 shows an example of a CCD layout. The horizontal register contains 28 dummy pixels that occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines at the front of the readout and two at the back of the readout. The horizontal direction has four OB pixels in the front and 48 in the back. Figure 37 shows the basic sequence layout to use during the effective pixel readout. The 48 OB pixels at the end of each line are used for the CLPOB signals.
AD9974 ANALOG FRONT END DESCRIPTION AND OPERATION 0.1µF 0.1µF REFB REFT 0.4V 1.4V AD9974 DC RESTORE SHP PBLK (WHEN DCBYP = 1) SHP SHD 0.1µF CCDIN DOUT PHASE INTERNAL VREF 2V FULL SCALE 6dB ~ 42dB S11 –3dB, 0dB, +3dB, +6dB S22 PBLK 1S1 2S2 CDS GAIN REGISTER CLI VGA GAIN REGISTER DAC PRECISION TIMING GENERATION DOUT OPTICAL BLACK CLAMP DIGITAL FILTER CLPOB 14 CLPOB PBLK IS NORMALLY CLOSED. IS NORMALLY OPEN.
AD9974 (N) SIGNAL SAMPLE Input Configurations (N) RESET SAMPLE The CDS circuit samples each CCD pixel twice to extract the video information and reject low frequency noise (see Figure 39). There are three possible configurations for the CDS: inverting CDS mode, noninverting CDS mode, and SHA mode. The CDSMODE register (Address 0x00[9:8]) selects which configuration is used. (N + 1) RESET SAMPLE VDD RESET LEVEL (VRST ) 05955-041 SHP SIGNAL LEVEL (VFS) CCDINP SHA1 Figure 41.
AD9974 SHA Mode—Differential Input Configuration Referring to Figure 46 and Table 19, the CCDINM signal is a constant dc voltage set at a level above ground potential. The sensor signal is applied to the other input, and samples are taken at the signal minimum and at a point of signal maximum. The resulting differential signal is the difference between the signal and the reference voltage. This configuration uses a differential input sample/hold amplifier (SHA) (see Figure 43).
AD9974 Variable Gain Amplifier Optical Black Clamp The VGA stage provides a gain range of approximately 6 dB to 42 dB, programmable with 10-bit resolution through the serial digital interface. A gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB.
AD9974 APPLICATIONS INFORMATION RECOMMENDED POWER-UP SEQUENCE 5. When the AD9974 is powered up, the following sequence is recommended (see Figure 48 for each step). 6. 1. 2. 3. 4. Turn on the power supplies for the AD9974 and apply CLI clock. There is no required sequence for turning on each supply. Although the AD9974 contains an on-chip power-on reset, a software reset of the internal registers is recommended.
AD9974 Example Register Settings for Power-Up The following settings can be used for basic operation. A single CLPOB pulse is used with only H-pattern and one field. Additional HPATS and FIELDS can be added, as needed, along with different CLPOB toggle positions.
AD9974 VD tVDHD HD 3ns MIN CLI 3ns MIN tCLIDLY SHD INTERNAL HD INTERNAL H-COUNTER RESET 11.5 CYCLES X X X X X X X X X X X X X X 0 1 2 NOTES 1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE. 2. INTERNAL H-COUNTER IS ALWAYS RESET 11.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE. 3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 12 OR 13 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE. 4.
AD9974 STANDBY MODE OPERATION The AD9974 contains two standby modes to optimize the overall power dissipation in a particular application. Bit 1 and Bit 0 of Address 0x00 control the power-down state of the device.
AD9974 CIRCUIT CONFIGURATION The AD9974 recommended circuit configuration is shown in Figure 51. Achieving good image quality from the AD9974 requires careful attention to PCB layout. All signals should be routed to maintain low noise performance. The CCD_A and CCD_B output signals should be directly routed to Pin A1 and Pin A7, respectively, through a 0.1 μF capacitor.
AD9974 3V IOVDD SUPPLY 1.8V LDO OUTPUT A RG_A OUTPUT RG_A DRIVER SUPPLY A8 CCDINP_B AVDD_B A7 RGVDD_B CCDINM_B A6 C9 C10 RGVSS_B 0.1µF 0.1µF RG_B A10 B10 GND GND LDO_OUT_B B9 B6 C6 GND GND GND D6 E6 E5 GND GND D5 C5 IOVDD_B 0.1µF 0.1µF 0.1µF IOVDD_A GND B5 A5 B3 B4 LDO_OUT_A 0.1µF RG_A RGVSS_A RGVDD_A C4 A1 C3 CCDINM_A 0.1µF D9 F7 G1 F8 H1 G7 J1 H7 K1 J7 G2 K7 H2 G8 K2 H8 3V DRIVER 3V DRIVER Figure 51. Recommended Circuit Configuration Rev.
AD9974 3-WIRE SERIAL INTERFACE TIMING All of the internal registers of the AD9974 are accessed through a 3-wire serial interface. Each register consists of a 12-bit address and a 28-bit data-word. Both the 12-bit address and 28-bit dataword are written starting with the LSB. To write to each register, a 40-bit operation is required, as shown in Figure 52. Although many registers are fewer than 28 bits wide, all 28 bits must be written for each register.
AD9974 LAYOUT OF INTERNAL REGISTERS The AD9974 address space is divided into two register areas, as shown in Figure 54. In the first area, Address 0x00 to Address 0x72 contain the registers for the AFE, miscellaneous functions, VD/HD parameters, I/O control, mode control, timing core, and update control functions. The second area of the address space, beginning at Address 0x800, consists of the registers for the H-pattern groups and fields.
AD9974 • UPDATING OF REGISTER VALUES The internal registers of the AD9974 are updated at different times, depending on the particular register. Table 21 summarizes the three types of register updates. The tables in the Complete Register Listing section also contain a column with update type to identify when each register is updated. • SCK Updated—Some of the registers are updated immediately as the 28th data bit (D27) is written.
AD9974 COMPLETE REGISTER LISTING All addresses and default values are expressed in hexadecimal. When an address contains less than 28 data bits, all remaining bits must be written as 0s. All TESTMODE registers must be set to the specified values. Table 22.
AD9974 Address 0x0C 0x0D Data Bit Content [27:0] [0] Default Value 0 0 0 0x0E 0x0F [3:1] [27:4] [27:0] [27:0] Update VD VD Name TESTMODE CLIDIVIDE SCK SCK TESTMODE Unused Unused Unused Description Test Operation Only. Set to 0 if this register is accessed. CLI Divide. 1 = divide CLI input frequency by 2. Test Operation Only. Set to 0. Set unused bits to 0. Set unused register to 0 if accessed. Set unused register to 0 if accessed. Table 23.
AD9974 Table 25. I/O Control Registers Address 0x23 0x24 0x25 0x26 0x27 Data Bit Content [0] [1] [2] Default Value 0 0 0 [3] [4] [7:5] [27:8] [27:0] [27:0] [27:0] [27:0] 0 0 1 Update SCK 0 0 0 0 Name TESTMODE TESTMODE IO_NVR DATA_NVR TESTMODE HCLKMODE Unused TESTMODE TESTMODE TESTMODE TESTMODE Description Test Operation Only. Set to 0. Test Operation Only. Set to 0. IOVDD Voltage Range for VD, HD, SCK, SDATA, and SL. 0 = 1.8 V. 1 = 3.3 V.
AD9974 Table 27.
AD9974 Address 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D Data Bit Content [10:8] [11] [14:12] [15] [18:16] [19] [22:20] [27:23] [5:0] [11:6] [17:12] [27:18] [5:0] [11:6] Default Value 1 Update Unused Unused Unused Unused Unused Unused Unused Description H3 Drive Strength. Set unused bits to 0. H4 Drive Strength. Set unused bits to 0. Test Operation Only. Set to 0. Set unused bits to 0. RG Drive Strength. Set unused bits to 0. SHD Sampling Edge Location. SHP Sampling Edge Location. SHP Width.
AD9974 Table 29.
AD9974 Address 0x05 0x06 0x07 0x08 0x09 0xA 0xB 0xC 0xD 0xE 0xF Data Bit Content [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [12:0] [27:13] [2:0] [5:3] [8:6] [11:9] [14:12] [17:15] [19:18] Default Value X X X X X X X X X X X X X X X [20] [27:21] [12:0] [20:13] [21] [22] [27:23] [12:0] [25:13] [27:26] [27:0] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] X X X X X X X X X X X X X X X X X X X X X X X Update SCP SCP SCP SCP SCP SCP SCP SCP SCP
AD9974 Address 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0xA 0xB 0xC 0xD 0xE 0xF Data Bit Content [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [12:0] [27:13] [4:0] [9:5] [14:10] [19:15] [24:20] [27:25] [4:0] [9:5] [14:10] [19:15] [27:20] [27:0] [8:0] [17:9] Default Value X X X X X X X X X X X X X X X X X X X X X [27:18] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [8:0] [17:9] X X X X X X X X X X X [27:18] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [12:0] [25:13] [2
AD9974 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 9.10 9.00 SQ 8.90 10 9 8 7 6 5 4 3 2 1 A B BALL A1 PAD CORNER TOP VIEW C D 7.20 BSC SQ E F G H J K 0.80 BSC DETAIL A 1.40 MAX DETAIL A 0.65 MIN 0.25 MIN SEATING PLANE COPLANARITY 0.12 COMPLIANT TO JEDEC STANDARDS MO-205-AB. 012006-0 0.55 0.50 0.45 BALL DIAMETER Figure 56.
AD9974 NOTES Rev.
AD9974 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05955-0-10/09(A) Rev.
