4-Bit, CCD Signal Processor with Precision Timing Core AD9979 FEATURES GENERAL DESCRIPTION 1.
AD9979 TABLE OF CONTENTS Features .............................................................................................. 1 Complete Field—Combining H-Patterns ............................... 23 Applications ....................................................................................... 1 Mode Registers ........................................................................... 24 General Description .........................................................................
AD9979 SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD (AFE, Timing Core) RGVDD (RG, HL Drivers) HVDD (H1 to H4 Drivers) DVDD (Internal Digital Supply) DRVDD (Parallel Data Output Drivers ) IOVDD (I/O Supply Without the Use of LDO) POWER SUPPLY CURRENTS—65 MHz OPERATION AVDD (1.8 V) RGVDD (3.3 V, 20 pF RG Load, 20 pF HL Load) HVDD1 (3.3 V, 200 pF Total Load on H1 to H4) DVDD (1.8 V) DRVDD (3.0 V) IOVDD (1.
AD9979 TIMING SPECIFICATIONS CL = 20 pF, AVDD = DVDD = 1.8 V, fCLI = 65 MHz, unless otherwise noted. Table 2.
AD9979 DIGITAL SPECIFICATIONS IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD = 2.7 V to 3.6 V, CL = 20 pF, tMIN to tMAX, unless otherwise noted. Table 3.
AD9979 ANALOG SPECIFICATIONS AVDD = 1.8 V, fCLI = 65 MHz, typical timing specifications, tMIN to tMAX, unless otherwise noted. Table 4. Parameter CDS1 Allowable CCD Reset Transient CDS Gain Accuracy −3.
AD9979 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter AVDD DVDD DRVDD IOVDD HVDD RGVDD Any VSS RG Output H1 to H4, HL Output SCK, SL, SDI REFT, REFB, CCDINM, CCDINP Junction Temperature Lead Temperature (10 sec) With Respect To AVSS DVSS DRVSS DVSS HVSS RGVSS Any VSS RGVSS HVSS DVSS AVSS Rating −0.3 V to +2.2 V −0.3 V to +2.2 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to RGVDD + 0.3 V −0.3 V to HVDD + 0.3 V −0.3 V to IOVDD + 0.3 V −0.
AD9979 48 47 46 45 44 43 42 41 40 39 38 37 D1 D0 (LSB) DVDD DVSS HD VD GPO2 GPO1 SCK SDI SL LDOEN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9979 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 REFB REFT AVDD AVSS CCDINM CCDINP AVDD AVSS CLI LDOOUT IOVDD RG 05957-003 D12 (MSB) D13 NC H1 H2 HVSS HVDD H3 H4 RGVSS HL RGVDD NC = NO CONNECT PIN 1 INDICATOR 13 14 15 16 17 18 19 20 21 22 23 24 D2 1 D3 2 D4 3 D5 4 D6 5 DRVSS 6 DRVDD 7 D7 8 D8 9 D9 10 D10 11 D11 12 NOTES 1.
AD9979 Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 Mnemonic CLI AVSS AVDD CCDINP CCDINM AVSS AVDD REFT REFB LDOEN SL SDI SCK GPO1 GPO2 VD HD DVSS DVDD D0 (LSB) D1 EPAD Type1 DI P P AI AI P P AO AO DI DI DI DI DIO DIO DI DI P P DO DO Description Master Clock Input Analog Ground for AFE Analog Supply for AFE (1.8 V) CCD Signal Positive Input CCD Signal Negative Input; Normally Tied to AVSS Analog Ground for AFE Analog Supply for AFE (1.
AD9979 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 250 0.8 200 0.6 0.4 150 0.2 LSB POWER (mW) TOTAL POWER 3.3V SUPPLIES 100 0 –0.2 –0.4 50 –0.6 1.8V SUPPLIES –0.8 55 60 65 0 160 8 140 6 120 4 100 2 LSB 10 80 –2 40 –4 20 –6 5 10 15 20 25 30 6k 8k 10k ADC OUTPUT CODE 12k 14k 16k 14k 16k 0 60 35 VGA GAIN (dB) 40 45 05957-065 RMS OUTPUT NOISE (LSB) 180 0 4k Figure 6. Differential Nonlinearity (DNL) Figure 4. Power vs.
AD9979 EQUIVALENT INPUT/OUTPUT CIRCUITS IOVDD AVDD 330Ω AVSS 05957-012 AVSS 05957-010 R DVSS Figure 8. CCD Input Figure 10. Digital Inputs HVDD OR RGVDD DATA OUTPUT ENABLE IOVDD 330Ω CLI 100kΩ HVSS OR RGVSS Figure 9. CLI Input, Register 0x15[0] =1 Enables the Bias Circuit Figure 11. H1 to H4, HL, and RG Outputs Rev.
AD9979 THEORY OF OPERATION All AD9979 clocks are synchronized with VD and HD inputs. All of the horizontal pulses (CLPOB, PBLK, and HBLK) of the AD9979 are programmed and generated internally. V DRIVER V1 > Vx, VSG1 > VSGx, SUBCK H1 TO H4, HL, RG The H drivers for H1 to H4 and RG are included in the AD9979, allowing these clocks to be directly connected to the CCD. The H-drive voltage of 3 V is supported in the AD9979.
AD9979 PROGRAMMABLE TIMING GENERATION Using a 65 MHz CLI frequency, the edge resolution of the Precision Timing core is approximately 240 ps. If a 1× system clock is not available, it is also possible to use a 2× reference clock, by programming the CLIDIVIDE register (Address 0x0D). The AD9979 then internally divides the CLI frequency by 2. PRECISION TIMING HIGH SPEED TIMING CORE The AD9979 generates flexible high speed timing signals using the Precision Timing core.
AD9979 1 2 H1, H3 4 3 H2, H4 05957-019 H1 TO H4 PROGRAMMABLE LOCATIONS: 1H1 RISING EDGE. 2H1 FALLING EDGE. 3H2 RISING EDGE. 4H2 FALLING EDGE. Figure 17. HCLK Mode 2 Operation 1 2 H1 H2 3 4 H3 H4 05957-020 H1 TO H4 PROGRAMMABLE LOCATIONS: 1H1 RISING EDGE. 2H1 FALLING EDGE. 3H3 RISING EDGE. 4H3 FALLING EDGE. Figure 18.
AD9979 Table 8. HCLK Modes (Selected by Register Address 0x23, Bits[7:5]) HCLK Mode Register Value Description Mode 1 Mode 2 001 010 Mode 3 100 Invalid Selection 000, 011, 101, 110, 111 H1 edges are programmable; H3 = H1, H2 = H4 = inverse of H1. H1 edges are programmable; H3 = H1. H2 edges are programmable; H4 = H2. H1 edges are programmable; H2 = inverse of H1. H3 edges are programmable; H4 = inverse of H3. Invalid register settings. Table 9.
AD9979 HORIZONTAL CLAMPING AND BLANKING The horizontal clamping and blanking pulses of the AD9979 are fully programmable to suit a variety of applications. Individual control is provided for CLPOB, PBLK, and HBLK during the different regions of each field. This allows the dark-pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate the different image transfer timing and high speed line shifts.
AD9979 Table 10.
AD9979 Individual HBLK Patterns HBLK Mode 0 Operation The HBLK programmable timing shown in Figure 23 is similar to CLPOB and PBLK; however, there is no start polarity control. Only the toggle positions designate the start and the stop positions of the blanking period. Additionally, as shown in Figure 24, there is a polarity control, HBLKMASK, for H1/H3 and H2/H4 that designates the polarity of the horizontal clock signals during the blanking period.
AD9979 Name HBLKTOGO1 HBLKTOGO2 HBLKTOGO3 HBLKTOGO4 HBLKTOGO5 HBLKTOGO6 HBLKTOGE1 HBLKTOGE2 HBLKTOGE3 HBLKTOGE4 HBLKTOGE5 HBLKTOGE6 RAxHyREPz1 Length 13 bits 13 bits 13 bits 13 bits 13 bits 13 bits 13 bits 13 bits 13 bits 13 bits 13 bits 13 bits 12 bits Range 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location
AD9979 Increasing Horizontal Clock Width During HBLK HBLK Mode 0 and HBLK Mode 1 allow the H1 to H4 pulse width to increase during the HBLK interval. As shown in Figure 27, the horizontal clock frequency can reduce by a factor of 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30 (see Table 12). To enable this feature, the HCLK_WIDTH register (Address 0x34, Bits[7:4]) is set to a value between 1 and 15. When this register is set to 0, the wide HCLK feature is disabled.
AD9979 HBLK Mode 2 Operation Figure 28 shows the example HBLK Mode 2 allows more advanced HBLK pattern operation. If unevenly spaced, multiple areas of HCLK pulses are needed; therefore, use HBLK Mode 2. Using a separate set of registers, HBLK Mode 2 can divide the HBLK region into up to six different repeat areas (see Table 11). As shown in Figure 28, each repeat area shares a common group of toggle positions, HBLKSTARTA, HBLKSTARTB, and HBLKSTARTC.
AD9979 HBLK, PBLK, and CLPOB Toggle Positions Note that toggle positions cannot be programmed during the 12-cycle delay from the HD falling edge until the horizontal counter has reset. See Figure 31 for an example of this restriction. The AD9979 uses an internal horizontal pixel counter to position the HBLK, PBLK, and CLPOB toggle positions. The horizontal counter does not reset to 0 until 12 CLI periods after the falling edge of HD.
AD9979 COMPLETE FIELD—COMBINING H-PATTERNS H-Pattern Selection After creating the H-patterns, they combine to create different readout fields. A field consists of up to nine different regions determined by the SCP registers, and within each region, a different H-pattern group can be selected, up to a maximum of 32 groups. Registers to control the H-patterns are located in the field registers. Table 13 describes the field registers. The H-patterns are stored in the HPAT memory, as described in Table 33.
AD9979 MODE REGISTERS To select the final field timing of the AD9979, use the mode registers. Typically, all of the field and H-pattern group information is programmed into the AD9979 at startup. During operation, the mode registers allows the user to select any combination of field timing to meet the current requirements of the system. The advantage of using the mode registers in conjunction with preprogrammed timing is that it greatly reduces the system programming requirements during camera operation.
AD9979 H-PATTERN MEMORY FIELD 0 FIELD 1 FIELD 2 FIELD 3 EXAMPLE 1: TOTAL FIELDS = 3, FIRST FIELD = FIELD 0, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 2 FIELD_SEL1 = 0 FIELD 0 FIELD_SEL2 = 1 FIELD 1 FIELD_SEL3 = 2 FIELD 2 EXAMPLE 2: TOTAL FIELDS = 1, FIRST FIELD = FIELD 3 FIELD_SEL1 = 3 FIELD 3 EXAMPLE 3: TOTAL FIELDS = 4, FIRST FIELD = FIELD 5, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 4, FOURTH FIELD = FIELD 2 FIELD 5 FIELD_SEL2 = 1 FIELD 1 FIELD_SEL3 = 4 FIELD 4 FIELD_SEL4 = 2 FIELD 2 05
AD9979 Figure 34 shows an example of a CCD layout. The horizontal register contains 28 dummy pixels, which occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines at the front of the readout and 2 OB lines at the back of the readout. The horizontal direction has 4 OB pixels in the front and 48 in the back. clamping sequences. It is important to use CLPOB only during valid OB pixels.
AD9979 GENERAL-PURPOSE OUTPUTS (GPO) GP Toggles The AD9979 provides programmable outputs to control a mechanical shutter, strobe/flash, the CCD bias select signal, or any other external component with general-purpose (GP) signals. Two GP signals are available, with up to two toggles each, that can be programmed and assigned to GPO1 and GPO2. These pins are bidirectional and also allow visibility of CLPOB, PBLK, and internal high speed signals (as an output) and external control of HBLK (as an input).
AD9979 Table 16. GPO Registers (Address 0x52 to Address 0x59) Name GP1_PROTOCOL GP2_PROTOCOL Length 2 bits 2 bits Range 0 to 3 0 to 3 GP_LINE_MODE 2 bits Off/on GPx_POL1 GPO_OUTPUT_EN 2 bits 2 bits Low/high Off/on SEL_GPOx1 2 bits 0 to 3 SEL_HS_GPOx1 2 bits 0 to 3 HBLK_EXT GP_LUT_EN GP12_LUT 1 bit 2 bits 4 bits Off/on Logic setting GPTx_TOGy_FIELD1, 2 GPTx_TOGy_LINE1, 2 GPTx_TOGy_PIXEL1, 2 4 bits 13 bits 13 bits 0 to 15 0 to 8191 0 to 8191 1 2 Description 0x0 = idle.
AD9979 Single-Field Toggles VD Single-field toggles begin in the field following the register write. There can be up to two toggles in the field. The mode is set with GPx_PROTOCOL equal to 1. In this mode, the field toggle settings must be set to 1. Toggles repeat for each field until GPx_PROTOCOL is set to 0. GPx_PROTOCOL must be reset to 0 for one field before it can be active again.
AD9979 ShotTimer Sequences Address 0x52 dictates the behavior of the LUT and identifies which signals receive the result. Each 4-bit register can realize any logic combination of GPO1 and GPO2. Table 17 shows how the register values of GP12_LUT[13:10] are determined. XOR, NAND, AND, and OR results are shown, but any 4-bit combination is possible. A simple example of XOR gating is shown in Figure 41. ShotTimer technology provides internal delay of scheduled toggles. The delay is in terms of fields.
AD9979 ANALOG FRONT-END DESCRIPTION AND OPERATION 0.1µF 0.1µF REFB REFT 0.4V 1.4V AD9979 DC RESTORE SHP PBLK (WHEN DCBYP = 1) SHP SHD 0.1µF CCDINP INTERNAL VREF 2V FULL SCALE 6dB TO 42dB S11 –3dB, 0dB, +3dB, +6dB S22 PBLK 1S1 2S2 VGA GAIN REGISTER CDS GAIN REGISTER DAC CLPOB PRECISION TIMING GENERATION 14 DOUT D0 TO D13 OPTICAL BLACK CLAMP CLPOB PBLK DIGITAL FILTER IS NORMALLY CLOSED. IS NORMALLY OPEN.
AD9979 (N) SIGNAL SAMPLE Input Configurations (N) RESET SAMPLE The CDS circuit samples each CCD pixel twice to extract the video information and to reject the low frequency noise (see Figure 43). There are three possible configurations for the CDS: inverting CDS mode, noninverting CDS mode, and SHA mode. CDSMODE (Address 0x00[9:8]) selects which configuration is used (see Table 24). (N + 1) RESET SAMPLE VDD RESET LEVEL (VRST) 05957-047 SHP SIGNAL LEVEL (VFS) CCDINP Figure 45.
AD9979 SHA Mode—Differential Input Configuration AD9979 In this configuration, which uses a differential input sampleand- hold amplifier (SHA), a signal is applied to the CCDINP input, while an inverse signal is applied simultaneously to the CCDINM input (see Figure 47). Sampling occurs on both signals at the same time, creating the differential output for amplification and for the ADC (see Figure 48 and Table 20). CCDINP IMAGE SENSOR SHA/ CDS 05957-051 CCDINM NOTES 1.
AD9979 Variable Gain Amplifier (VGA) Optical Black Clamp The VGA stage provides a gain range of approximately 6 dB to 42 dB, programmable with 10-bit resolution through the serial digital interface. A gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB.
AD9979 APPLICATIONS INFORMATION RECOMMENDED POWER-UP SEQUENCE 4. When the AD9979 is powered up, the following sequence is recommended (refer to Figure 52 for each step). 5. 1. 2. 3. Turn on the power supplies for the AD9979 and apply CLI clock. There is no required order for bringing up each supply. Although the AD9979 contains an on-chip, power-on reset, a software reset of the internal registers is recommended.
AD9979 Example Register Settings for Power-Up The following settings can be used for basic operation. A single CLPOB pulse is used with only H-pattern and one field. Additional HPATS and FIELDS can be added, as needed, along with different CLPOB toggle positions.
AD9979 VD tVDHD HD tHDCLI CLI tCLISHP tCLIDLY SHPLOC INTERNAL SHDLOC INTERNAL HD INTERNAL H-COUNTER RESET H-COUNTER (PIXEL COUNTER) X X X X X X X X X X X X X X 0 1 2 NOTES 1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHPLOC (INTERNAL SAMPLING EDGE). 2. INTERNAL H-COUNTER IS ALWAYS RESET 11.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE, AT SHDLOC (INTERNAL SAMPLING EDGE). 3.
AD9979 Table 22. Standby Mode Operation I/O Block AFE Timing Core H1 H2 H3 H4 HL RG DOUT Total Shutdown (Default)1, 2 Off Off High-Z High-Z High-Z High-Z High-Z High-Z Low3 OUT_CONTROL = Low2 No change No change Low High Low High Low Low Low Reference Standby Only REFT, REFB on On Low (4.3 mA) High (4.3 mA) Low (4.3 mA) High (4.3 mA) Low (4.3 mA) Low (4.
AD9979 1.8V LDOOUT 0.1µF 2 GENERAL-PURPOSE OUTPUTS 3 SERIAL INTERFACE +3V 39 38 37 43 42 41 40 NC DVDD DVSS HD VD GPO2 GPO1 SCK SDI SL LDOEN 48 47 46 45 44 NC VD/HD/HBLK INPUTS 2 0.1µF (LSB) D0 D1 D2 D3 D4 DRVSS 3V DRIVER SUPPLY + 4.7µF 0.1µF 1 PIN 1 INDICATOR 36 REFB 0.1µF 0.1µF 35 REFT 2 3 4 5 6 0.1µF 34 AVDD 33 AVSS 32 CCDINM 31 CCDINP AD9979 DRVDD 7 D5 8 0.1µF 30 AVDD 29 AVSS + 0.1µF D6 9 28 CLI D7 10 27 LDOOUT D8 11 26 IOVDD D9 12 25 RG CCD SIGNAL PLUS 1.
AD9979 3-WIRE SERIAL INTERFACE TIMING Figure 57 shows a more efficient way to write to the registers, using the AD9979 address auto-increment capability. Using this method, the lowest desired address is written first, followed by multiple 28-bit data-words. Each new 28-bit data-word is automatically written to the next highest register address. By eliminating the need to write to each 12-bit address, faster register loading is achieved.
AD9979 LAYOUT OF INTERNAL REGISTERS The AD9979 address space is divided into two different register areas, as illustrated in Figure 58. In the first area, Address 0x000 to Address 0x7FF contain the registers for the AFE, miscellaneous functions, VD/HD parameters, input/output control, mode control, timing core, test, and update control functions. The second area of the address space, beginning at Address 0x800, consists of the registers for the H-pattern groups and fields.
AD9979 UPDATING OF NEW REGISTER VALUES VD Updated (VD) The internal registers of the AD9979 are updated at different times, depending on the register. Table 23 summarizes the three different types of register updates. The register listing tables also contain a column with update type to identify when each register is updated (see Table 24 to Table 34). Many of the registers are updated at the next VD falling edge.
AD9979 COMPLETE REGISTER LISTING All addresses and default values are expressed in hexadecimal. When an address contains less than 28 data bits, all remaining bits must be written as 0s. Table 24.
AD9979 Address 07 08 09 0A 0B 0C 0D Data Bit Content [27:0] [27:0] [27:0] [27:0] [27:0] [27:0] [0] Default Value 0 0 0 0 0 0 0 0 0E 0F [3:1] [27:4] [27:0] [27:0] Update Type VD Name TESTMODE TESTMODE TESTMODE TESTMODE TESTMODE TESTMODE CLIDIVIDE TESTMODE Unused Unused Unused Description Test operation only. Set to 0. Test operation only. Set to 0. Test operation only. Set to 0. Test operation only. Set to 0. Test operation only. Set to 0. Test operation only. Set to 0. CLI divide.
AD9979 Table 26. VD/HD Registers Default Value 0 Update Type 21 Data Bit Content [0] [27:1] [0] 0 SCK 0 22 [2:1] [27:3] [27:0] Address 20 Name TESTMODE Unused VDHDPOL TESTMODE Unused TESTMODE 0 Description Test operation only. Set to 0. Set unused bits to 0. VD/HD active polarity. 0 = active low. 1 = active high. Test operation only. Set to 0. Set unused bits to 0. Test operation only. Set to 0. Table 27.
AD9979 Table 29.
AD9979 Address 35 36 37 38 39 3A 3B 3C 3D Data Bit Content [2:0] Default Value 1 Update Type SCK Name H1DRV [3] [6:4] [7] [10:8] [11] [14:12] [15] [18:16] [19] [22:20] [27:23] [5:0] [11:6] [17:12] [27:18] [5:0] [11:6] 0 20 10 SCK 0 20 SCK [12] 0 DCLKMODE [14:13] 2 CLKDATA_SEL [15] 0 INV_DCLK [27:16] [27:0] [27:0] [27:0] [27:0] [27:0] [27:0] 1 1 1 1 1 Unused H2DRV Unused H3DRV Unused H4DRV Unused HLDRV Unused RGDRV Unused SHDLOC SHPLOC SHPWIDTH Unused DOUTPHASEP DOUTPHASEN Unused Unu
AD9979 Table 30. Test Registers—Do Not Access Address 3E 3F 40 41 to 4F Data Bit Content [18:0] [27:19] [27:0] [3:0] [9:4] [27:10] [27:0] Default Value 4B020 Update Type F 0 Name TESTMODE Unused Unused TESTMODE TESTMODE Unused Unused Description Test operation only. Set to 4B020. Set unused bits to 0. Set unused register to 0, if accessed. Test operation only. Set to F, if accessed. Test operation only. Set to 0. Set unused bits to 0. Set unused registers to 0, if accessed. Table 31.
AD9979 Address 53 54 55 56 57 58 59 5A to 5F 1 2 3 Data Bits [1:0] Default Value 0 [3:2] 0 SEL_GPO1 [5:4] [7:6] 0 0 SEL_GPO2 SEL_HS_GPO1 [9:8] [10] [27:11] [3:0] [12:4] [25:13] [27:26] [12:0] [16:13] [27:19] [12:0] [25:13] [27:25] [3:0] [12:4] [25:13] [27:26] [12:0] [16:13] [27:19] [12:0] [25:13] [27:25] [27:0] 0 0 SEL_HS_GPO2 HBLK_EXT Unused GPT1_TOG1_FIELD Unused GPT1_TOG1_LINE Unused GPT1_TOG1_PIXEL GPT1_TOG2_FIELD Unused GPT1_TOG2_LINE GPT1_TOG2_PIXEL Unused GPT2_TOG1_FIELD Unused GPT2
AD9979 Table 32.
AD9979 Address 67 Data Bit Content [15:0] 68 to 72 [27:16] [27:0] Default Value 0000 Update Type SCK Name TGCORE_UPDT_VD Unused Unused Description Enable VD update of timing core registers. Each bit corresponds to one address location. TGCORE_UPDT_VD[0] = 1; update Address 0x30 on VD rising edge. TGCORE_UPDT_VD[1] = 1; update Address 0x31 on VD rising edge. … TGCORE_UPDT_VD[15] = 1; update Address 0x37 on VD rising edge. Set unused bits to 0, if accessed. Set unused registers to 0, if accessed.
AD9979 Address 08 09 0A 0B 0C 0D 0E 0F 1 Data Bit Content [2:0] [5:3] [8:6] [11:9] [14:12] [17:15] [19:18] Default Value 1 X X X X X X X [20] [27:21] [12:0] [20:13] [21] [22] [27:23] [12:0] [25:13] [27:26] [27:0] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] X Update Type SCP X X X X SCP X X SCP X X X SCP X X SCP X X SCP X X SCP Name HBLKALT_PAT1 HBLKALT_PAT2 HBLKALT_PAT3 HBLKALT_PAT4 HBLKALT_PAT5 HBLKALT_PAT6 HBLKMODE TESTMODE Unused H
AD9979 Address 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 1 Data Bit Content [12:0] [27:13] [4:0] [9:5] [14:10] [19:15] [24:20] [27:25] [4:0] [9:5] [14:10] [19:15] [27:20] [27:0] [8:0] [17:9] [27:18] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [8:0] [17:9] [27:18] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] [12:0] [25:13] [27:26] Default Value1 X Update Type VD X X X X X VD X X X X VD X X VD X X VD X X VD X X VD X X VD X X VD X X VD X X VD Name SCP8 Un
AD9979 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 37 36 PIN 1 INDICATOR 0.50 BSC 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 13 12 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP SEATING PLANE 1 EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 12° MAX 48 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 080108-A TOP VIEW 1.00 0.85 0.
AD9979 NOTES Rev.
AD9979 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05957-0-10/09(C) Rev.
