High Performance 10-Bit Display Interface AD9984A FEATURES Advanced TVs Plasma display panels LCDTV HDTV RGB graphics processing LCD monitors and projectors Scan converters AD9984A 10 AUTO OFFSET AUTO GAIN Pr/REDIN1 Pr/REDIN0 2:1 MUX CLAMP 10 AUTO OFFSET AUTO GAIN Y/GREENIN1 Y/GREENIN0 2:1 MUX CLAMP 10-BIT ADC PGA 10 AUTO OFFSET AUTO GAIN Pb/BLUEIN1 Pb/BLUEIN0 HSYNC1 HSYNC0 VSYNC0 VSYNC1 SOGIN1 SOGIN0 2:1 MUX CLAMP PGA 10-BIT ADC SCL 10 10 2:1 MUX 2:1 MUX Y/GREENOUT Cb/BLUEOUT
AD9984A TABLE OF CONTENTS Features .............................................................................................. 1 Output Formatter ....................................................................... 21 Applications....................................................................................... 1 2-Wire Serial Control Port ............................................................ 22 Functional Block Diagram ..............................................................
AD9984A SPECIFICATIONS ANALOG INTERFACE CHARACTERISTICS VD = 1.8 V, VDD = 3.3 V, PVD = 1.8 V, DAVDD = 1.8 V, ADC clock = maximum conversion rate, full temperature range = 0°C to 70°C. Table 1.
AD9984A Parameter POWER SUPPLY VD Supply Voltage VDD Supply Voltage PVD Supply Voltage DAVDD Supply Voltage VD Supply Current (ID) VDD Supply Current (IDD) PVD Supply Current (IPVD) DAVDD Supply Current (IDAVDD) Total Power Dissipation Power-Down Supply Current Power-Down Dissipation DYNAMIC PERFORMANCE Analog Bandwidth, Full Power Crosstalk 1 2 Temp Test Level 1 Full Full Full Full 25°C 25°C 25°C 25°C Full Full Full IV IV IV IV V V V V VI VI VI 25°C Full V V AD9984AKSTZ-140 AD9984AKCPZ-140 Min Typ M
AD9984A ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VD VDD PVD DAVDD Analog Inputs REFHI REFLO Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature EXPLANATION OF TEST LEVELS Rating 1.98 V 3.6 V 1.98 V 1.98 V VD to 0.0 V VD to 0.0 V VD to 0.0 V 5 V to 0.0 V 20 mA −25°C to +85°C −65°C to +150°C 150°C 150°C I. 100% production tested. II. 100% production tested at 25°C and sample tested at specified temperatures.
AD9984A BLUE 2 BLUE 1 BLUE 0 VDD (3.3V) GND SDA SCL HSYNC1 VSYNC1 HSYNC0 VSYNC0 EXTCK/COAST CLAMP PVD (1.8V) GND PVD (1.8V) GND FILT PVD (1.8V) GND PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 BLUE 3 59 BLUE 4 3 58 BLUE 5 BAIN1 4 57 BLUE 6 VD (1.8V) 5 56 BLUE 7 GAIN0 6 55 BLUE 8 GND 7 54 BLUE 9 SOGIN0 8 53 GND VD (1.8V) 9 52 VDD (3.3V) 51 GREEN 0 50 GREEN 1 SOGIN1 12 49 GREEN 2 VD (1.
RED 0 RED 1 RED 2 RED 3 RED 4 RED 5 RED 6 RED 7 RED 8 RED 9 VDD DATACK SOGOUT HSOUT VSOUT/A0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 O/E FIELD 47 REFHI 3 46 REFLO GREEN 6 4 45 PWRDN GREEN 5 5 44 RAIN1 GREEN 4 6 43 RAIN0 GREEN 3 7 42 VD 41 SOGIN1 40 GAIN1 GREEN 0 10 39 VD BLUE 9 11 38 SOGIN0 BLUE 8 12 37 GAIN0 BLUE 7 13 36 VD BLUE 6 14 35 BAIN1 BLUE 5 15 34 BAIN0 BLUE 4 16 33 VD 25 26 27 28 29 30 31 32 PVD 24
AD9984A Pin Type Outputs References Power Supply Control 1 2 Pin Number 80-Lead LQFP 64-Lead LFCSP 28 to 37 54 to 63 42 to 51 1 to 10 54 to 63 11 to 20 25 52 23 50 22 49 24 51 21 48 78 31 18 46 20 47 1, 5, 9, 13 33, 36, 39, 42 26, 38, 52, 64 21, 53 74, 76, 79 30, 32 41 64 3, 7, 11, 15, 27, N/A 39, 40, 53, 65, 75, 77, 80 66 22 67 23 22 49 Mnemonic RED[9:0] GREEN[9:0] BLUE[9:0] DATACK HSOUT VSOUT 2 SOGOUT O/E FIELD FILT REFLO REFHI VD VDD PVD DAVDD GND Function Outputs of Converter R; Bit 9 is the MSB
AD9984A Table 5.
AD9984A Mnemonic FILT Function External Filter Connection HSOUT Horizontal Sync Output VSOUT/A0 Vertical Sync Output (VSOUT) Serial Port Address Input 0 (A0) SOGOUT Sync-On-Green Slicer Output O/E FIELD SDA SCL RED[9:0] GREEN[9:0] BLUE[9:0] Odd/Even Field Bit for Interlaced Video Serial Port Data I/O Serial Port Data Clock Data Output, Red Channel Data Output, Green Channel Data Output, Blue Channel DATACK Data Clock Output VD (1.8 V) Main Power Supply VDD (1.8 V to 3.
AD9984A The AD9984A is a fully integrated solution for capturing and digitizing analog RGB or YPbPr signals for display on advanced TVs, flat panel monitors, projectors, and other types of digital displays. Implemented in a high performance CMOS process, the interface can capture signals with pixel rates up to 170 MHz.
AD9984A In systems with embedded sync, a blacker-than-black signal (Hsync) is briefly produced to signal the CRT that it is time to begin a retrace. Because the input is not at black level at this time, it is important to avoid clamping during Hsync. Fortunately, there is usually a period following Hsync (called the back porch) where a good black reference is provided. This is the time when clamping should be done.
AD9984A The ability to program a target code offers a large degree of freedom and flexibility. Although all channels are set to either 1 or 512 in most cases, the flexibility to select other values makes it possible to insert intentional skews between channels. It also allows the ADC range to be skewed so that voltages outside of the normal range can be digitized. For example, setting the target code to 40 allows the sync tip, which is normally below black level, to be digitized and evaluated.
AD9984A CLOCK GENERATION A PLL is used to generate the pixel clock. The Hsync input provides a reference frequency to the PLL. A voltage controlled oscillator (VCO) generates a much higher pixel clock frequency. The pixel clock is divided by the PLL divide value (Register 0x01 and Register 0x02) and phase-compared with the Hsync input. Any error is used to shift the VCO frequency and maintain lock between the two signals.
AD9984A The polarity of the coast signal can be set through the coast polarity register (Register 0x18, Bits[6:5]). In addition, the polarity of the Hsync signal can be set through the Hsync polarity register (Register 0x12, Bits[5:4]). For both Hsync and coast, a value of 1 is active high. The internal coast function is driven off the Vsync signal, which is typically a time when Hsync signals can be disrupted with extra equalization pulses. Table 10.
AD9984A SYNC PROCESSING The inputs of the sync processing section of the AD9984A are combinations of digital Hsyncs and Vsyncs, analog sync-ongreen or sync-on-Y signals, and an optional external coast signal. From these signals, the part generates a precise, jitterfree clock from its PLL, an odd/even-field signal, HSOUT and VSOUT signals, a count of Hsyncs per Vsync, and a programmable SOGOUT.
AD9984A Sync Slicer Hsync Filter and Regenerator The purpose of the sync slicer is to extract the sync signal from the green graphics or luminance video signal that is connected to the SOG input. The sync signal is extracted in a two step process. First, the SOG input is clamped to its negative peak, (typically 0.3 V below the black level). Next, the signal goes to a comparator with a variable trigger level (set by Register 0x1D, Bits[7:3]), but nominally 0.128 V above the clamped level.
AD9984A HSYNCIN FILTER WINDOW HSYNCOUT VSYNC EQUALIZATION PULSES EXPECTED EDGE 06476-010 FILTER WINDOW Figure 11. Sync Processing Filter SYNC SEPERATOR THRESHOLD Vsync Filter and Odd/Even Fields The filter works by examining the placement of Vsync with respect to Hsync and if necessary, shifting it in time slightly. The goal is to keep the Vsync and Hsync leading edges from switching at the same time, thus eliminating confusion as to when the first line of a frame occurs.
AD9984A POWER MANAGEMENT To meet display requirements for low standby power, the AD9984A includes a power-down mode. The power-down state can be controlled manually (via Pin 17 or Register 0x1E, Bit 3), or automatically by the chip. If automatic control is selected (Register 0x1E, Bit 4 =1), the AD9984A’s decision is based on the status of the following sync detect bits in Register 0x24: Bit 2, Bit 3, Bit 6, and Bit 7.
AD9984A DATAIN P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 HSYNCx DATACK 8 CLOCK CYCLE DELAY DATAOUT P0 P1 P2 P3 06476-014 2 CLOCK CYCLE DELAY HSOUT Figure 15. 4:4:4 Timing Mode DATAIN P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 HSYNCx DATACK 8 CLOCK CYCLE DELAY YOUT Cb/CrOUT Y0 Y1 Y2 Y3 CB0 CR0 CB2 CR2 2 CLOCK CYCLE DELAY HSOUT 06476-015 NOTES 1. PIXEL AFTER HSOUT CORRESPONDS TO BLUE INPUT. 2. EVEN NUMBER OF PIXEL DELAY BETWEEN HSOUT AND DATAOUT. Figure 16.
AD9984A COAST TIMING OUTPUT FORMATTER In most computer systems, the Hsync signal is provided continuously on a dedicated wire. In these systems, the COAST input and function are unnecessary and should not be used. The output formatter is capable of generating several output formats to be presented to the 30 data output pins. The output formats and the pin assignments for each format are listed in Table 12. In addition, there are several clock options for the output clock.
AD9984A 2-WIRE SERIAL CONTROL PORT A 2-wire serial control interface is provided with the AD9984A. Up to two AD9984A devices can be connected to the 2-wire serial interface with each device having a unique address. The 2-wire serial interface comprises a clock (SCL) and a bidirectional data (SDA) pin. The analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface.
AD9984A Serial Interface Read/Write Examples Write to One Control Register Read from One Control Register 1. Start signal 1. Start signal 2. Slave address byte (R/W bit = low) 2. Slave address byte (R/W bit = low) 3. Base address byte 3. Base address byte 4. Start signal 4. Data byte to base address 5. Slave address byte (R/W bit = high) 5. Stop signal 6. Data byte from base address Write To Four Consecutive Control Registers 7. Stop signal 1.
AD9984A 2-WIRE SERIAL REGISTER MAP The AD9984A is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 14.
AD9984A Hex Address Read/Write, Read Only Bits 6 Default Value *0** **** 5 **0* **** 4 ***1 **** 3 **** 1*** Register Name 0x13 R/W 7:0 0010 0000 Hsync Duration 0x14 R/W 7 0*** **** Vsync Control 6 *0** **** 5 **0* **** 4 ***1 **** 3 **** 1*** 2 **** *0** 1 **** **0* Description Hsync Source Select. Determines the source of the Hsync for PLL and sync processing. This bit is used only if Reg. 0x12, Bit 7 is set to 1 or if both syncs are active.
AD9984A Hex Address Read/Write, Read Only Bits 3 Default Value **** 0*** 2 **** *0** 1 **** **0* **** ***0 0000 1000 Clamp Placement Register Name 0x19 R/W 0 7:0 0x1A R/W 7:0 0010 0000 Clamp Duration 0x1B R/W 7 0*** **** Clamp and Offset 6 *1** **** 5 **0* **** 4:3 ***1 1*** 0x1C R/W 2:0 7:0 **** *011 1111 1111 Test Register 0 0x1D R/W 7:3 0111 1*** SOG Control 2 **** *0** 1:0 **** **00 7 *** **** 6 *0** **** 5 **1* **** 4 ***1 **** 3 **** 0*** 0x1E R/W
AD9984A Hex Address Read/Write, Read Only Bits 2 Default Value **** *0** 1 **** **0* 0 **** ***0 7:5 100* **** 4 ***1 **** 3 **** 0*** 2:1 **** *10* 0 **** ***0 7:6 0*** **** 5 *0** **** 4 **0* **** 3 ***0 **** 2 **** 1*** 1 **** *0** 0x21 R/W 0 7:0 **** ***0 0010 0000 Description Power-Down Pin Polarity. Sets the polarity of the signal on the PWRDN pin. 0 = PWRDN polarity is negative. 1 = PWRDN polarity is positive. Power-Down Fast Switching Control.
AD9984A Hex Address 0x25 Read/Write, Read Only RO Bits 6 Default Value *_** **** 5 **_* **** 4 ***_ **** 3 **** _*** 2 **** *_** 1 **** **_* 0 **** ***_ 7 _*** **** 6 *_** **** 5 **_* **** 4 ***_ **** 3 **** _*** 2 **** *_** 1 **** **_* 0 **** ***_ 0x26 RO 7:0 0x27 RO 7:4 0x28 R/W 7:0 0x29 R/W 7:0 0x2A 0x2B 0x2C RO RO R/W 7:0 7:0 7:5 Register Name Sync Polarity Detect Description HSYNC1 Detection. 0 = HSYNC1 is not active. 1 = HSYNC1 is active.
AD9984A Hex Address Read/Write, Read Only Bits 4 Default Value ***0 **** R/W 3:0 7:0 **** 0000 1111 0000 Test Register 5 Description Auto-Offset Hold. Disables the auto-offset and holds the feedback result. 0 = Continuous update. 1 = One time update. Must be written to default for proper operation. Must be written to 0xE8 for proper operation. 0x2D 0x2E R/W 7:0 1111 0000 Test Register 6 Must be written to 0xE0 for proper operation.
AD9984A 2-WIRE SERIAL CONTROL REGISTERS CHIP IDENTIFICATION Table 15. VCO Range Select Bits 0x00—Bits[7:0] Chip Revision Value 00 01 10 11 This is an 8-bit register that represents the silicon revision. PLL DIVIDER CONTROL 0x01—Bits[7:0] PLL Divide Ratio MSBs Result (Pixel Rates) 10 to 31 31 to 62 62 to 124 124 to 170 These are the 8 MSBs of the 12-bit PLL divide ratio (PLLDIV). The PLL derives a pixel clock from the incoming Hsync signal.
AD9984A 0x05—Bits[6:0] Red Channel Gain Control MSBs 0x0C—Bits[7:5] Red Channel Offset Control LSBs This register contains the 7-bit MSBs of the red channel gain control. Values written to this register are not updated until the LSB register (Register 0x06) has also been written to. The power-up default is 1000000. This register contains the 3-bit LSBs of the red channel offset control. Combining these bits with the 8 bits of MSBs in Register 0x0B creates 11 bits of offset control.
AD9984A 0x12—Bit[5] Hsync Input Polarity Override 0x14—Bit[6] Vsync Source Select This bit determines whether the chip selects the Hsync input polarity or if it is specified. Setting this bit to 0 allows the chip to automatically select the polarity of the input Hsync. Setting it to 1 indicates that Bit 4 of Register 0x12 specifies the polarity. Power-up default is 0. This bit selects the source of the Vsync for sync processing only if Bit 7 of Register 0x14 is set to 1.
AD9984A 0x14—Bit[1] Vsync Duration Block Enable 0x18—Bit[5] Input Coast Polarity This enables the Vsync duration block, which is designed to be used with the Vsync filter. Setting the bit to 0 leaves the Vsync output duration unchanged. Setting the bit to 1 sets the Vsync output duration based on Register 0x15. Power-up duration is 0. This register sets the input coast polarity when Bit 6 of Register 0x18 is 1. The power-up default setting is 1. Table 29.
AD9984A 0x19—Bits[7:0] Clamp Placement Table 39. Auto-Offset Enable Bit An 8-bit register that sets the position of the internally generated clamp. When clamp source select = 0 (Register 0x18, Bit 4), a clamp signal is generated internally at a position established by this register and for a duration set by the clamp duration register (Register 0x1A). Clamping is started at the clamp placement count of pixel periods after the trailing edge of Hsync.
AD9984A INPUT AND POWER CONTROL 0x1E—Bit[3] Power-Down 0x1E—Bit[7] Channel Select Override This bit is used to manually place the chip in power-down mode. It is only used if manual power-down control is selected (Register 0x1E, Bit 4 = 0). Both the state of this register bit and the power-down pin (Pin 17) are used to control manual power-down. (See the Power Management section for more details on power-down.) This bit provides an override to the automatic input channel selection.
AD9984A Table 51. Output Mode Bits Table 56. Output Clock Select Bits Value 100 101 110 Value 00 01 10 11 Result 4:4:4 RGB mode. 4:2:2 YCbCr mode. 4:4:4 DDR mode. 0x1F—Bit[4] Primary Output Enable This bit places the primary output in active or high impedance mode. The power-up default setting is 1. Table 52. Primary Output Enable Bit Value 0 1 Result Normal outputs. All outputs (except SOGOUT) in high impedance mode.
AD9984A 0x20—Bit[0] Table 65. VSYNC1 Detection Bit Must be set to 1 for proper operation. Value 0 1 0x21—Bits[7:0] Must be set to default. Result No activity detected. Activity detected. 0x24—Bit[3] SOGIN0 Detection 0x22—Bits[7:0] This bit is used to indicate when activity is detected on the SOGIN0 pin. If SOGIN0 is held high or low, activity is not detected. Figure 9 shows where this function is implemented. Must be set to default.
AD9984A 0x25—Bit[6] HSYNC1 Polarity HSYNC COUNT This bit indicates the polarity of HSYNC1 input. 0x26—Bits[7:0] Hsyncs per Vsync MSBs Table 71. HSYNC1 Polarity Bit This register contains the 8 MSBs of the 12-bit counter that reports the number of Hsyncs per Vsync on the active input. It is useful for determining the mode and is an aid in setting the PLL divide ratio. Value 0 1 Result HSYNC1 polarity is negative. HSYNC1 polarity is positive.
AD9984A 0x2E—Bits[7:0] Test Register 6 Read/write bits for future use. Must be written to 0xE0 for proper operation. 0x34—Bit[2] SOG Filter Enabler When this bit is set to 1, the SOG does not pass pulses less than 250 ns in width. This reduces spurious signals that can improperly drive the PLL circuit. Default for this bit is 0 or off. 0x36—Bit[0] VCO Gear Select This bit allows the VCO to select a lower gear to run lower pixel clocks while remaining in a more linear range.
AD9984A PCB LAYOUT RECOMMENDATIONS The AD9984A is a high precision, high speed, analog device. To achieve the maximum performance from the part, it is important to have a well laid-out board. The section provides a guide for designing a board using the AD9984A. ANALOG INTERFACE INPUTS Use the following layout techniques on the graphics inputs: • • • • • Minimize the trace length running into the graphics inputs.
AD9984A DIGITAL INPUTS Reference Bypass Digital inputs on the AD9984A (HSYNC0, HSYNC1, VSYNC0, VSYNC1, SOGIN0, SOGIN1, SDA, SCL, and CLAMP) are designed to work with 3.3 V signals, but are tolerant of 5 V signals. Therefore, no extra components need to be added if using 5 V logic. The AD9984A has two reference voltages that must be bypassed for proper operation of the ADC. REFLO and REFHI are connected to each other through a 10 μF capacitor.
AD9984A OUTLINE DIMENSIONS 0.75 0.60 0.45 16.20 16.00 SQ 15.80 1.60 MAX 61 80 60 1 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.10 COPLANARITY 20 41 40 21 VIEW A VIEW A 0.65 BSC LEAD PITCH 0.38 0.32 0.22 051706-A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BEC Figure 20. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters 9.00 BSC SQ 0.60 MAX 8.
AD9984A NOTES Rev.
AD9984A NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06476-0-7/07(0) Rev.
