Datasheet

AD9985
Rev. 0 | Page 18 of 32
Hex
Address
Write and
Read or
Read Only Bits
Default
Value Register Name Function
*****0**
Bit 2 – Red Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
******0*
Bit 1 – Green Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
*******0
Bit 0 – Blue Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
11H R/W 7:0 00100000
Sync Separator
Threshold
Sync Separator Threshold. Sets how many internal 5 MHz clock periods
the sync separator will count to before toggling high or low. This
should be set to some number greater than the maximum Hsync or
equalization pulsewidth.
12H R/W 7:0 00000000 Pre-Coast
Pre-Coast. Sets the number of Hsync periods that Coast becomes
active prior to Vsync.
13H R/W 7:0 00000000 Post-Coast
Post-Coast. Sets the number of Hsync periods that Coast stays active
following Vsync.
14H RO 7:0 Sync Detect
Bit 7 – Hsync detect. It is set to Logic 1 if Hsync is present on the
analog interface; otherwise it is set to Logic 0.
Bit 6 – AHS: Active Hsync. This bit indicates which analog Hsync is
being used. (Logic 0 = Hsync Input Pin, Logic 1 = Hsync from Sync-on-
Green.)
Bit 5 – Input Hsync Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
Bit 4 – Vsync Detect. It is set to Logic 1 if Vsync is present on the analog
interface; otherwise it is set to Logic 0.
Bit 3 – AVS: Active Vsync. This bit indicates which analog Vsync is
being used. (Logic 0 = Vsync Input Pin, Logic 1 = Vsync from Sync
Separator.)
Bit 2 – Output Vsync Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
Bit 1 – Sync-on-Green Detect. It is set to Logic 1 if sync is present on
the Green video input; otherwise it is set to 0.
Bit 0 – Input Coast Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
15H
R/W
7:2 111111** Reserved
Bits [7:2] Reserved for future use. Must be written to 111111 for proper
operation.
1 ******1* Output Formats
Bit 1 – 4:2:2 Output Formatting Mode (Logic 0 = 4:2:2 mode, Logic 1=
4:4:4 mode)
0 *******1 Reserved Bit 0 – Must be set to 0 for proper operation.
16H
R/W
7:0 Test Register Reserved for future use.
17H RO 7:0 Test Register Reserved for future use.
18H RO 7:0 Test Register Reserved for future use.
19H
R/W
7:0 00000100 Red Target Code Target Code for Auto Offset Operation.
1AH
R/W
7:0 00000100
Green Target
Code
Target Code for Auto Offset Operation.
1BH
R/W
7:0 00000100
Blue Target
Code
Target Code for Auto Offset Operation.
1CH
R/W
7:0 00010001 Reserved Must be written to 11h for proper operation.
1DH
R/W
7 0*******
Auto Offset
Enable
Enables the auto offset circuitry.
6 *0****** Hold Auto Offset Holds the offset output of the auto offset at the current value.
5:2 **1001** Reserved Must be written to 9 for proper operation.
1:0 ******10 Update Mode Changes the update rate of the auto offset.
1EH
R/W
7:0 0000**** Test Register Must be set to default value.
*The AD9985 updates the PLL divide ratio only when the LSBs are written to (Register 02H).