Datasheet

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Quad Pin Timing Formatter

ADATE207

Rev. 0

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FEATURES

4-channel timing formatter

256 waveforms per channel

4 independent event edges per waveform

STIL IEEE 1450-1999-compatible events

4-period range for each edge

39.06 ps timing resolution

2.5 ns minimum edge refire rate

All drive formats supported

100 MHz base vector rate

×2 and ×4 high speed modes

×2 pin multiplexing

1 ns minimum pulse width

32-bit fail counter per channel

4-bit pin capture per channel

Air cooled, low power CMOS design

6 W at 100 MHz base rate

2.5 V power supply

Differential DCL interface control

TMU multiplexer

APPLICATIONS

Automatic test equipment (ATE)

High speed digital instrumentation

Pulse generation

FUNCTIONAL BLOCK DIAGRAM

TIME SET

MEMORY

FORMAT

COMPARE

LOGIC

QUAD EDGE

GENERATOR

FAIL

DETECTION

PATTERN

FAIL

DCL

INTERFACE

TIME SET

MEMORY

FORMAT

COMPARE

LOGIC

QUAD EDGE

GENERATOR

FAIL

DETECTION

PATTERN

FAIL

DCL

INTERFACE

TIME SET

MEMORY

FORMAT

COMPARE

LOGIC

QUAD EDGE

GENERATOR

FAIL

DETECTION

PATTERN

FAIL

DCL

INTERFACE

TIME SET

MEMORY

FORMAT

COMPARE

LOGIC

QUAD EDGE

GENERATOR

FAIL

DETECTION

PATTERN

FAIL

DCL

INTERFACE

ADATE207

05557-001

Figure 1.

GENERAL DESCRIPTION

The ADATE207 is a timing generator and formatter for auto-

matic test equipment (ATE) equipment. The ADATE207 provides

four independent channels with a 100 MHz base vector rate of

timing and formatting for ATE digital pins. It interfaces between

the pattern memory,and the driver, comparator, and load (DCL)

chips for complete digital pins. The ADATE207 accepts up to

eight bits of pattern data per pin and can produce formatted

outputs and perform comparisons of DUT expected responses.

Each channel of the ADATE207 provides 256 selectable wave-

forms, wherein each waveform consists of up to four possible

events. Each event consists of a programmable timing edge and a

STIL-compatible (IEEE Standard 1450-1999) set.

Each timing edge generator can produce an edge with a span of

four periods with a 39.06 ps edge placement resolution. The delay

generators use a reference master clock of 100 MHz and provide

programmable delays based upon counts of the clock and a

compensated CMOS analog timing vernier. The programmable

delay generators can be additionally delayed by a global 8-bit

input value that is shared across all edges.

The format and compare logic support ×2 pin multiplexing to

allow the trading of pin count for speed.

Each channel provides a 4-bit DUT output capture supporting

mixed signal receive memory applications. The fail detection

logic includes a 32-bit fail accumulation register per channel.

An external TMU is supported with three 8-to-1 multiplexers.

This allows the dual comparator outputs of any pin to be

multiplexed to any of the three outputs: arm, start, or stop

signals.

Summary of content (36 pages)

PAGE 1
Quad Pin Timing Formatter ADATE207 FEATURES APPLICATIONS Automatic test equipment (ATE) High speed digital instrumentation Pulse generation GENERAL DESCRIPTION The ADATE207 is a timing generator and formatter for automatic test equipment (ATE) equipment. The ADATE207 provides four independent channels with a 100 MHz base vector rate of timing and formatting for ATE digital pins. It interfaces between the pattern memory,and the driver, comparator, and load (DCL) chips for complete digital pins.
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ADATE207 TABLE OF CONTENTS Features .............................................................................................. 1 Drive and Compare Logic......................................................... 13 Applications....................................................................................... 1 Pipeline Considerations............................................................. 14 Functional Block Diagram ..............................................................
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ADATE207 SPECIFICATIONS DC SPECIFICATIONS TC = 85°C ± 5°C, VDD = 2.5 V, unless otherwise noted. Table 1.
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ADATE207 AC SPECIFICATIONS TC = 85°C ± 5°C, VDD = 2.5 V, unless otherwise noted. Table 2.
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ADATE207 TIMING DIAGRAMS MCLK_P MCLK_N DIGITAL INPUTS tISU tIH DIGITAL OUTPUTS 05557-007 tOCO(MIN) tOCO(MAX) Figure 2. Timing Diagram for Inputs and Outputs JTAG JTAG INPUT tJSU tJH 05557-015 JTAG OUTPUT tJCO Figure 3. Timing Diagram for Scan Inputs and Scan Outputs MCLK_P MCLK_N BIDIRECTIONAL (WRITES) tBSU tBH tBCZV BIDIRECTIONAL (READS) tBCO(MIN) tBCZ Figure 4. Timing Diagram for Bidirectional Reads and Writes Rev.
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ADATE207 ABSOLUTE MAXIMUM RATINGS BYPASSING SCHEME Table 3. Parameter VDD Digital Inputs Resistor Termination pins Resistor Termination Current Termination Pad Current Junction Temperature Storage Temperature Rating −0.3 V to +2.8 V −0.3 V to VDD + 0.3 V −0.3 to VDD + 0.3 V 12 mA max 12 mA max 125°C −40 to 125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
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ADATE207 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C CH0 DCL I/F PATTERN DATA D E PERIOD DATA CH1 DCL I/F F ADATE207 G H CH2 DCL I/F COMPARE FAILS ADATE207 RECEIVE DATA BOTTOM VIEW (Not to Scale) CH3 DCL I/F J K L M N P 05557-009 COMMAND/ STATUS BUS TIME MEASUREMENT R T U Y Figure 5. Connection Overview Diagram 05557-014 V W Figure 6. Ball Grid Array Table 7. Pin Function Descriptions Pin No.
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ADATE207 Pin No.
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ADATE207 Pin No.
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ADATE207 Pin No.
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ADATE207 Pin No. Y20 to Y18, Y12, Y11, Y8, Y3 to Y1, W20, W1, V20, V1, N20, N1, K20, K1, J20, J1, C20, C1, B20, B1, A20 to A18, A13, A10, A9 W19, W18, W3, W2, V19, V18, V3, V2, U17, U14, U11, U7, U4, P17, P4, K17, K4, G17, G4, D17, D14, D10, D7, D4, C19, C18, C3, C2, B19, B18, B3, B2 1 Mnemonic VSS Input/Output 1 P Type GND Description Power, 0.0 V. VDD P VDD Power, 2.5 V. A = analog, D = differential, I = input, O = output, P = power. Rev.
PAGE 12
ADATE207 THEORY OF OPERATION WAVEFORM MEMORY Table 8. STIL-Compatible Events Pattern data is used to address the waveform memory and is eight bits wide per channel, supporting 256 unique waveforms. The data width of the waveform memory is 26 bits wide per event or 104 bits wide per pin. The waveform memory data bits are partitioned into two fields, a 22-bit wide delay field, and a 4-bit event code field. The waveform memory is dual port allowing CPU access during pattern bursting.
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ADATE207 per pin with individual fail counters. Fail outputs are resynchronized to T0 and output for fail processing. 2.5 2.0 Fails can be masked on a per edge basis and match mode is supported. Masking of failures prevents incrementing of the fail counter and the setting of the accumulated fail registers. It does not prevent the fail signals from reflecting the comparison state of the expect edge. Strobe comparison fails are associated with the timing edge that generates the strobe.
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ADATE207 INPUT_DELAY M M PAT_PATDATA T0 PIPELINE REGISTER MCLK PIPELINE REGISTER DUT 4 4 11 T0 M C CLK400 PIPELINE REGISTER 1 PROGRAMMABLE RTD DELAY [0:31] 11 FIFO 2 C C C C RTD COMPENSATION M C 1 PROGRAMMABLE T0 DELAY [0:30] 3 T0 T0 T0 FAIL DUTDATA 05557-002 T0 LEGEND Figure 8.
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ADATE207 D PER_EARLY_T0EN PER_EARLY_C0EN Q CE M M comparator outputs of the digital pins to the time measurement unit signals, TMU_ARM, TMU_START, and TMU_STOP. Offchip control logic must select the appropriate TMU bus output signal from the ADATE207 and direct its selection to the TMU. The TMU outputs are high speed, differential 8 mA drivers and can be tristated for bus applications.
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ADATE207 After the power and MCLK inputs are stable, the device must be reset using the hard reset and error reset bits. The soft reset can be used to initialize registers at any time and does not reset the PLL or FIFOs. Rule 3—after MCLK is stable, keep the hard reset pin (RESET_B) asserted for at least 20 μs. There are six rules of reset. Rule 5—the hard reset signal (RESET_B) can be asserted asynchronously to MCLK, but upon deassertion, must make setup and hold requirements upon the MCLK.
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ADATE207 COMP_CH0_P TEMPERATURE DIODE 50Ω COMP_CH0_T 100µA COMP_CH0_N TDIODE DIFFERENTIAL LVPECL INPUT TEMPERATURE DIODE FORCE I, MEASURE V 05557-006 50Ω Figure 14. Differential Input with Termination Resistors 05557-017 EXTERNAL TERMINATION REQUIRED ADATE207 50Ω ADATE207 VOP Figure 12. Block Diagram of Temperature Diode 50Ω VON 740 ESD ESD 720 680 8mA 660 05557-019 POTENTIAL (mV) 700 640 Figure 15.
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ADATE207 CONTROL AND STATUS REGISTER INTERFACE The ADATE207 uses a general-purpose, 16-bit bidirectional, multiplexed address data bus for computer access of the control and status registers of the part. All bus activity is registered at the interface synchronous to the master clock (MCLK), which is also used by the part for delay timing. Operations the bus supports include random access reads and writes, as well as the ability to access blocks of registers in burst.
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ADATE207 MCLK CYCLES ASSERTED FOR 2 OR MORE CYCLES WILL ALLOW 1 EXTRA CYCLE OF READ DATA HOLD ON BUS (OPTIONAL) CS_AS CS_RW_B A1 WD1 A2 WD2 A3 RD3 1 CYCLE OF BUS TURN-AROUND + 8 CYCLES OF READ DATA DELAY A4 WD4 1 CYCLE OF BUS TURN-AROUND 05557-010 CS_AD Figure 16. Bus Interface Function Timing Diagram ADATE207. Note that the read data takes more than one clock cycle. The bus interface state machine controls the output enable accordingly.
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ADATE207 MCLK CYCLES CS_AS CS_AS LOW ENDS BURST CS_RW_B BA WD1 WD2 WD3 WD4 WD5 WD6 WD7 WD8 RA RD 05557-011 CS_AD BURST ADDRESS CYCLE INITIATES BURST Figure 17. Write Burst Mode Functional Timing MCLK CYCLES CS_AS LOW ENDS BURST CS_AS CS_RW_B BA RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 1 CYCLE OF BUS TURN-AROUND + 8 CYCLES OF READ DATA DELAY A4 WD4 05557-012 CS_AD 1 CYCLE OF BUS TURN-AROUND Figure 18.
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ADATE207 CONTROL AND STATUS REGISTERS This section details the breakdown of the configuration and status registers in the ADATE207. An address map provides the locations of all registers, and the detailed descriptions that follow show how each register is used. Table 13. Address Map Chip Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 to 0x18 0x19 1x1A 0x1B 0x1C 0x1D 0x1E 0x1F Register Description Comparator and Fail Status.
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ADATE207 CHANNEL SPECIFIC AND COMMON REGISTERS Detailed register descriptions divided into channel-specific and common registers. Channel Specific Registers Name: Comparator and Fail Status Address: 0x00 Type: Read Table 14. Comparator and Fail Status Position Bits[15:08] Bit 07 Description Not used. Edge Error: Edges Longer Than 4 T0 Cycles. This occurs when the edge delay counters are reloaded before they complete counting down, thus, causing a missing edge. Edge Error: Out of Order Edge Strobes.
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ADATE207 Name: Fail Counter High Address: 0x02 Type: Read/Write Table 16. Fail Counter High Position Bits[15:00] Description Fail Counter Data High. This field contains the 16 MSBs of the fail counter. See Table 15, the fail counter low register, for more information. Name: Static Configuration Address: 0x03 Type: Read/Write Reset State 0x0000 Table 17. Static Configuration Position Bits[15:04] Bit 03 Bit 02 Bit 01 Bit 00 Description Not Used. Ch_Data_Low.
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ADATE207 Name: Dynamic Configuration Address: 0x04 Type: Read/Write Table 18. Dynamic Configuration Position Bits[15:05] Bit 04 Description Not Used. Edge Generation Enable. Low turns off the channel’s edge delay generators. High turns on the channel’s edge delay generators. T0 and C0 Select. Low selects T0 as the pattern cycle clock for the edge delay generators. High selects C0 as the pattern cycle clock for the edge delay generators.
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ADATE207 Name: Waveform D0 Vernier Delay and Action Address: 0x06 Type: Read/Write Table 20. Waveform D0 Vernier Delay and Action Position Bits[15:10] Bits[09:04] Bits[03:00] Description D0 Vernier Delay. The vernier delay is represented in binary by the equation, vvvvvv × (2.5 ns/64). Not Used. D0 Action. A binary encoded data field. 0x0 = no action. 0x1 = drive low. 0x2 = drive high. 0x3 = force off. 0x4 = force on. 0x5 = force down. 0x6 = force up. 0x7 = edge compare low. 0x8 = edge compare high.
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ADATE207 Name: Waveform D1 Vernier Delay and Action Address: 0x08 Type: Read/Write Table 22. Waveform D1 Vernier Delay and Action Position Bits[15:10] Bits[09:04] Bits[03:00] Description D1 Vernier Delay. The vernier delay is represented in binary by the equation, vvvvvv × (2.5 ns/64). Not Used. D1 Action. A binary encoded data field. 0x0 = no action. 0x1 = drive low. 0x2 = drive high. 0x3 = force off. 0x4 = force on. 0x5 = force down. 0x6 = force up. 0x7 = edge compare low. 0x8 = edge compare high.
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ADATE207 Name: Waveform D2 Vernier Delay and Action Address: 0x0A Type: Read/Write Table 24. Waveform D2 Vernier Delay and Action Position Bits[15:10] Description D2 Vernier Delay: The vernier delay is represented in binary by the equation, vvvvvv × (2.5 ns/64) Not Used. D2 Action. A binary encoded data field. 0x0 = no action. 0x1 = drive low. 0x2 = drive high. 0x3 = force off. 0x4 = force on. 0x5 = force down. 0x6 = force up. 0x7 = edge compare low. 0x8 = edge compare high. 0x9 = edge compare off.
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ADATE207 Name: Waveform D3 Vernier Delay and Action Address: 0x0C Type: Read/Write Table 26. Waveform D3 Vernier Delay and Action Position Bits[5:10] Bits[09:04] Description D3 Vernier Delay: The vernier delay is represented in binary by the equation, vvvvvv × (2.5 ns/64) Not Used. D3 Action: A binary encoded data field. 0x0 = no action. 0x1 = drive low. 0x2 = drive high. 0x3 = force off. 0x4 = force on. 0x5 = force down. 0x6 = force up. 0x7 = edge compare low. 0x8 = edge compare high.
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ADATE207 Name: Calibration Memory D1 Address: 0x0F Type: Read/Write Table 29. Calibration Memory D1 Position Bits[15:08] Bits[07:00] Description Not Used. D1 Calibration Constant (CCCCCCCC). The calibration delay is represented in binary by the equation CCCCCCCC × (2.5 ns/64) Name: Calibration Memory D2 Address: 0x10 Type: Read/Write Reset State 0x000 Undefined Table 30. Calibration Memory D2 Position Bits[15:08] Bits[07:00] Description Not Used. D2 Calibration Constant (CCCCCCCC).
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ADATE207 Position Bits[10:08] Description PAT_DUTDATA2 Select. A binary encoded data field that selects which edge and which comparator to drive out of the ADATE207 PAT_DUTDATAx[2] pin. 0x0 = Edge D0 low comparator. 0x1 = Edge D0 high comparator. 0x2 = Edge D1 low comparator. 0x3 = Edge D1 high comparator. 0x4 = Edge D2 low comparator. 0x5 = Edge D2 high comparator. 0x6 = Edge D3 low comparator. 0x7 = Edge D3 high comparator. Not Used PAT_DUTDATA1 Select.
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ADATE207 Position Bit 01 Description Fail Counters Clear. Writing a 1 to this bit creates a pulse to clear the fail counters for all channels. Writing a 0 has no affect. Soft Reset. Writing this register bit to a Logic 1 causes the ADATE207 to generate a software reset. This is logically equivalent to a hard reset via the I_RESET_B pin. All logic and registers are reset. Bit 00 Name: Round Trip Delay Value Address: 0x1A Type: Read/Write Reset State 0x0 0x0 Table 34.
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ADATE207 Position Description 0x0 selects Channel 0 comparator high. 0x1 selects Channel 0 comparator low. 0x2 selects Channel 1 comparator high. 0x3 selects Channel 1 comparator low. 0x4 selects Channel 2 comparator high. 0x5 selects Channel 2 comparator low. 0x6 selects Channel 3 comparator high. 0x7 selects Channel 3 comparator low. TMU Arm Enable. A zero tristates the TMU Stop output. TMU Arm Channel Select Multiplexer. A binary encoded data field. 0x0 selects Channel 0 comparator high.
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ADATE207 Position Bit 10 Description Channel 2 Timing Error. This indicates that the channel had a timing error. This signal is the Logic OR of the timing error flags of the channel. More details of the error can be found by reading the error flags for Channel 2. Channel 1 Timing Error. This indicates that the channel had a timing error. This signal is the Logic OR of the timing error flags of the channel. More details of the error can be found by reading the error flags for Channel 1.
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ADATE207 APPLICATION INFORMATION TIME MEASUREMENT SUPPORT The ADATE207 contains support for time measurement through an external time measurement unit (TMU) in the following ways: • Connect the high comparator output of any channel to TMU arm, TMU start, or TMU stop. • Connect the low comparator output of any channel to TMU arm, TMU start, or TMU stop. • Tristate the TMU multiplexer outputs using an enable control bit.
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ADATE207 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 27.00 BSC SQ 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 24.13 BSC SQ 2 1 A B C D E F G H J K L M N P R T U V W Y BALL A1 INDICATOR TOP VIEW 3 BOTTOM VIEW 1.27 BSC DETAIL A 1.00 0.80 0.60 DETAIL A 1.70 MAX 0.70 0.60 0.50 0.10 MIN 0.25 MIN (4×) 0.90 0.75 0.60 BALL DIAMETER COPLANARITY 0.20 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-192-BAL-2 Figure 25.