Low Noise Stereo Codec with Enhanced Recording and Playback Processing ADAU1381 FEATURES GENERAL DESCRIPTION 24-bit stereo audio ADC and DAC 400 mW speaker amplifier (into 8 Ω load) Built-in sound engine for audio processing Wind noise detection and autofiltering Enhanced stereo capture (ESC) Dual-band automatic level control (ALC) 6-band equalizer, including notch filter Sampling rates from 8 kHz to 96 kHz Stereo pseudo differential microphone input Optional stereo digital microphone input pulse-density
ADAU1381 TABLE OF CONTENTS Features .............................................................................................. 1 Input Signal Path ........................................................................ 30 Applications....................................................................................... 1 Analog-to-Digital Converters................................................... 31 General Description .........................................................................
ADAU1381 Pad Configuration.......................................................................70 Outline Dimensions........................................................................84 Digital Subsystem Configuration..............................................77 Ordering Guide ...........................................................................84 REVISION HISTORY 1/11—Rev. A to Rev. B Changes to Pin PDN Description in Table 10 .............................
ADAU1381 SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V, digital supply = 1.5 V, unless otherwise noted; temperature = 25°C; master clock (MCLK) = 12.
ADAU1381 Parameter Left/Right Microphone PGA Gain Range Left/Right Microphone PGA Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio DIFFERENTIAL MICROPHONE INPUT TO ADC PATH Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Left/Right Microphone PGA Mute Attenuation Interchannel Gain Mismatch Off
ADAU1381 Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Beep Input Mute Attenuation Offset Error Gain Error Interchannel Gain Mismatch Beep Input PGA Gain Range Beep Playback Mixer Gain Range Power Supply Rejection Ratio MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.90 × AVDD Bias Current Source Noise in the Signal Bandwidth Test Conditions/Comments −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V; mute set by Register 0x4008, Bit 3 AVDD = 3.3 V AVDD = 3.
ADAU1381 Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Gain Error Interchannel Gain Mismatch Offset Error DAC TO SPEAKER OUTPUT PATH Differential Full-Scale Output Voltage (0 dB) Total Harmonic Distortion + Noise 4 Ω Load 8 Ω Load Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS
ADAU1381 Parameter Total Harmonic Distortion + Noise Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Differential Offset Error Mono Mixer Mute Attenuation, Beep to Mixer Path Muted REFERENCE (CM PIN) Common-Mode Reference Output Test Conditions/Comments Min Typ Max Unit 8 Ω, 1 nF load, AVDD = 1.8 V, PO = 50 mW AVDD = 3.3 V, PO = 175 mW −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.
ADAU1381 TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, PLL is active in integer mode at a 256 × fS input rate for fS = 48 kHz, analog and digital input tones are −1 dBFS with a frequency of 1 kHz. Analog input and output are simultaneously active. Pseudo differential stereo input is routed to ADCs, and DACs are routed to stereo line output with a 16 kΩ load. ADC input at −1 dBFS, DAC input at 0 dBFS. The speaker output is disabled. The serial port is configured in slave mode.
ADAU1381 Parameter DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode Factor Min Typ 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value
ADAU1381 DIGITAL TIMING SPECIFICATIONS −25°C < TA < +85°C, IOVDD = 1.62 V to 3.63 V, unless otherwise specified. Table 7. Digital Timing Parameter MASTER CLOCK tMP Duty Cycle SERIAL PORT tBIL tBIH tLIS tLIH tSIS tSIH tSODM SPI PORT fCCLK,R fCCLK,R fCCLK,W fCCLK,W tCCPL tCCPH tCLS tCLH tCLPH tCDS tCDH tCOD I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tSCR tSCF tSDR tSDF tBFT DIGITAL MICROPHONE tDCF tDCR tDDV tDDH tMIN 50 30 Limit tMAX Unit Description 90.
ADAU1381 Digital Timing Diagrams tLIH tBIH BCLK tBIL tLIS LRCLK tSIS DAC_SDATA LEFT-JUSTIFIED MODE MSB MSB – 1 tSIH tSIS DAC_SDATA I2S MODE MSB tSIH tSIS tSIS DAC_SDATA RIGHT-JUSTIFIED MODE LSB MSB tSIH tSIH 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 08313-002 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 2.
ADAU1381 tCLS tCLH tCLPH tCCPL tCCPH CLATCH CCLK CDATA tCDH tCDS COUT 08313-004 tCOD Figure 4. SPI Port Timing tSDR tSCH tDS tSCH SDA tSDF tSCR SCL tSCLL tSCS tSCF tBFT 2 Figure 5. I C Port Timing tDCF tDCR CLK DATA1/ DATA2 DATA1 DATA2 tDDH tDDV tDDV DATA1 DATA2 Figure 6. Digital Microphone Timing Rev.
ADAU1381 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Power Supply (AVDD1 = AVDD2) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.9 V ±20 mA –0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −25°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
ADAU1381 32 31 30 29 28 27 26 25 MICBIAS BEEP LMIC/LMICN/MICD1 LMICP RMICP RMIC/RMICN/MICD2 AOUTL AOUTR PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADAU1381 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 NC AGND2 SPP NC SPN AVDD2 MCKO MCKI NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1381 GROUNDS.
ADAU1381 Table 10. Pin Function Descriptions Pin No.
ADAU1381 0 0.10 –10 0.08 –20 0.06 –30 0.04 MAGNITUDE (dBFS) –40 –50 –60 –70 0.02 0 –0.02 –0.04 –80 –0.06 –90 –0.08 –0.10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (NORMALIZED TO fS) 08313-009 –100 Figure 9. ADC Decimation Filter, 64× Oversampling, Normalized to fS 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 08313-012 MAGNITUDE (dBFS) TYPICAL PERFORMANCE CHARACTERISTICS 0.50 FREQUENCY (NORMALIZED TO fS) Figure 12.
0 0.05 –10 0.04 –20 0.03 –30 0.02 MAGNITUDE (dBFS) –40 –50 –60 –70 0.01 0 –0.01 –0.02 –80 –0.03 –90 –0.04 –0.05 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (NORMALIZED TO fS) 08313-015 –100 Figure 15. DAC Interpolation Filter, 64× Oversampling, Normalized to fS 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY (NORMALIZED TO fS) 08313-018 MAGNITUDE (dBFS) ADAU1381 Figure 18.
ADAU1381 0 0 –10 –20 –20 –40 THD + N (dB) THD + N (dB) –30 –50 –60 –40 –60 –70 –80 –80 –90 1 10 100 SPEAKER OUTPUT POWER (mW) 600 Figure 21. THD + N vs. Speaker Output Power, 8 Ω Load, 3.3 V Supply 1 10 SPEAKER OUTPUT POWER (mW) 100 08313-122 –100 08313-121 –100 Figure 22. THD + N vs. Speaker Output Power, 8 Ω Load, 1.8 V Supply Rev.
ADAU1381 SYSTEM BLOCK DIAGRAMS IOVDD 10µF AVDD1 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.1µF 49.9kΩ AVDD2 AVDD1 DVDDOUT 10µF IOVDD DIFFERENTIAL INPUT (LEFT) MICBIAS + 100pF LMIC/LMICN/MICD1 SPN LMICP SPP 10kΩ 10kΩ 10Ω 220µF AOUTL 10µF STEREO SINGLE-ENDED HEADPHONE OUTPUT 49.9kΩ 10kΩ ADAU1381 100pF DIFFERENTIAL INPUT (RIGHT) 10µF 10kΩ RMIC/RMICN/MICD2 49.
ADAU1381 IOVDD 10µF AVDD1 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.1µF 2kΩ AVDD2 AVDD1 DVDDOUT MICBIAS IOVDD MICBIAS + 100pF SPN 0.1µF 10kΩ SPP ANALOG MIC 1 LMIC/LMICN/MICD1 10µF 10kΩ LMICP AOUTR CM ADAU1381 ANALOG MIC 2 10kΩ 10kΩ 0.1µF 10kΩ 10kΩ 10Ω 220µF 10µF + RMIC/RMICN/MICD2 49.9kΩ LEFT_OUT 100pF MICBIAS 2kΩ 10Ω 220µF AOUTL CM + 49.
ADAU1381 IOVDD 10µF AVDD1 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.1µF AVDD2 AVDD1 DVDDOUT IOVDD MICBIAS + 100pF SPN SINGLE-ENDED STEREO INPUT 10kΩ SPP 10kΩ 10µF CM 49.9kΩ 10Ω 220µF AOUTL LMIC/LMICN/MICD1 AOUTR LMICP LEFT_OUT + 1kΩ STEREO SINGLE-ENDED HEADPHONE OUTPUT 10kΩ CM ADAU1381 100pF 10µF 1kΩ RMIC/RMICN/MICD2 10kΩ CM 49.
ADAU1381 IOVDD 10µF AVDD1 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.
ADAU1381 THEORY OF OPERATION The ADAU1381 is a low power audio codec with an integrated, fixed-function audio processing sound engine. It is an all-in-one package that offers high quality audio, low power, small size, and many advanced features. The stereo ADC and stereo DAC each have a dynamic range (DNR) performance of at least 96.5 dB and a total harmonic distortion plus noise (THD + N) performance of at least −90 dB.
ADAU1381 STARTUP, INITIALIZATION, AND POWER POWER-UP SEQUENCE This section details the procedure for setting up the ADAU1381 properly. Figure 27 provides an overview of how to initialize the IC. If AVDD1 and AVDD2 are from the same supply, they can power up simultaneously. If AVDD1 and AVDD2 are from separate supplies, then AVDD1 should be powered up first. IOVDD should be applied simultaneously with AVDD1, if possible.
ADAU1381 CLOCK GENERATION AND MANAGEMENT The ADAU1381 uses a flexible clocking scheme that enables the use of many different input clock rates. The PLL can be bypassed or used, resulting in two different approaches to clock management. For more information about clocking schemes, PLL configuration, and sampling rates, see the Clocking and Sampling Rates section. Case 1: PLL Is Bypassed If the PLL is bypassed, the core clock is derived directly from the master clock (MCLK) input.
ADAU1381 CLOCKING AND SAMPLING RATES SOUND ENGINE FRAME RATE fS / 0.5, 1, 1.5, 2, 3, 4, 6 CORE CLOCK AUTOMATICALLY SET TO 1024 × fS WHEN PLL CLOCK SOURCE SELECTED CONVERTER SAMPLING RATE ADCs DACs fS / 0.5, 1, 1.5, 2, 3, 4, 6 SERIAL PORT SAMPLING RATE SERIAL DATA INPUT/OUTPUT PORTS ADC_SDATA/GPIO1 fS / 0.5, 1, 1.
ADAU1381 Fractional Mode Table 14 and Table 15 list the sampling rate divisions for common base sampling rates. Fractional mode is used when the MCLK is a fractional (R + (N/M)) multiple of the PLL output. Table 14. Base Sampling Rate Divisions for fS = 48 kHz Base Sampling Frequency fS = 48 kHz For example, if MCLK = 12 MHz and fS = 48 kHz, then Sampling Rate Scaling fS/1 fS/6 fS/4 fS/3 fS/2 fS/1.5 fS/0.5 Sampling Rate 48 kHz 8 kHz 12 kHz 16 kHz 24 kHz 32 kHz 96 kHz Table 15.
ADAU1381 The ADC and DAC sampling rate can be set in Register 16407 (0x4017), Converter Control 0, Bits[2:0], converter sampling rate. The sound engine sampling rate and serial port sampling rate are similarly set in Register 16619 (0x40EB), sound engine frame rate, Bits[3:0], sound engine frame rate, and Register 16632 (0x40F8), serial port sampling rate, Bits[2:0], serial port control sampling rate, respectively. Table 18. Sampling Rates for 256 × 48 kHz Core Clock Core Clock 12.
ADAU1381 RECORD SIGNAL PATH Analog Beep Input BEEP PGA The BEEP pin is used for mono single-ended signals, such as a beep warning. This signal bypasses the ADCs and the sound engine and is mixed directly into any of the analog outputs. LMIC/LMICN/ MICD1 PGA LMICP A BEEP pin input can also be amplified or muted by a PGA, up to 32 dB in Register 16392 (0x4008), digital microphone and analog beep control. The beep input must be enabled in Register 16400 (0x4010), microphone bias control and beep enable.
ADAU1381 Digital ADC Volume Control LMIC/LMICN/ MICD1 PGA LMICP The ADC output (digital input) volume can be adjusted in Register 16410 (0x401A), left ADC attenuator, Bits[7:0], left ADC digital attenuator, for the left channel digital volume control and in Register 16411 (0x401B), right ADC attenuator, Bits[7:0], right ADC digital attenuator, for right channel digital volume control.
ADAU1381 PLAYBACK SIGNAL PATH LEFT PLAYBACK MIXER beep signal. The mixer can be controlled in Register 16415 (0x401F), playback mono mixer control. LINE OUT AMPLIFIER LEFT DAC AOUTL LEFT PLAYBACK BEEP GAIN MONO PLAYBACK BEEP GAIN BEEP FROM RECORD PGA The drivers are low noise, Class AB mono amplifiers designed to drive 8 Ω, 400 mW speakers. The output is differential and does not require external capacitors.
ADAU1381 CONTROL PORTS The ADAU1381 can operate in one of two control modes: I2C control or SPI control. The ADAU1381 has both a 4-wire SPI control port and a 2-wire I2C bus control port. Each can be used to set the registers. The part defaults to I2C mode but can be put into SPI control mode by pulling the CLATCH pin low three times. The control port is capable of full read/write operation for all addressable registers.
ADAU1381 Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, the ADAU1381 immediately jumps to the idle condition. During a given SCL high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition.
ADAU1381 I2C Read and Write Operations of the subaddress, the master must issue a repeated start command followed by the chip address byte with the R/W bit set to 1 (read). This causes the ADAU1381 SDA to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU1381. Figure 40 shows the timing of a single-word write operation. Every ninth clock pulse, the ADAU1381 issues an acknowledge by pulling SDA low.
ADAU1381 SPI PORT Data Bytes By default, the ADAU1381 is in I2C mode, but can be put into SPI control mode by pulling CLATCH low three times. The SPI port uses a 4-wire interface, consisting of CLATCH, CCLK, CDATA, and COUT signals, and is always a slave port. The CLATCH signal goes low at the beginning of a transaction and high at the end of a transaction. The CCLK signal latches CDATA on a low-to-high transition.
ADAU1381 CLATCH CDATA BYTE 0 BYTE 1 BYTE 2 08313-042 CCLK BYTE 3 Figure 44. SPI Write to ADAU1381 Clocking (Single-Write Mode) CLATCH CCLK COUT BYTE 1 BYTE 0 BYTE 3 HIGH-Z DATA Figure 45. SPI Read from ADAU1381 Clocking (Single-Read Mode) Rev.
ADAU1381 SERIAL DATA INPUT/OUTPUT PORTS The flexible serial data input and output ports of the ADAU1381 can be set to accept or transmit data in 2-channel format or in a 4-channel or 8-channel TDM stream to interface to external ADCs or DACs. Data is processed by default in twos complement, MSB first format, unless otherwise configured in the control registers. By default, the left channel data field precedes the right channel data field in 2-channel streams.
ADAU1381 LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK LSB MSB LSB MSB 08313-045 SDATA 1/fS 2 Figure 47. I S Mode—16 Bits to 24 Bits per Channel MSB LSB MSB LSB 08313-046 SDATA RIGHT CHANNEL LEFT CHANNEL LRCLK BCLK 1/fS Figure 48. Left-Justified Mode—16 Bits to 24 Bits per Channel RIGHT CHANNEL SDATA MSB LSB MSB LSB 08313-047 LEFT CHANNEL LRCLK BCLK 1/fS Figure 49.
ADAU1381 GENERAL-PURPOSE INPUT/OUTPUTS The serial data input/output pins are shared with the generalpurpose input/output function. Each of these four pins can be set to only one function. The function of these pins is set in Register 16628 (0x40F4), serial data/GPIO pin configuration. The GPIO pins can be used as either inputs or outputs. These pins are readable and can be set either through the control interface or directly by the sound engine.
ADAU1381 SOUND ENGINE SIGNAL PROCESSING The ADAU1381 is designed to provide a fixed-function signal processing flow specifically catered to digital still cameras and other low power applications. PROCESSING FLOW SigmaStudio is also capable of one-click generation of C-compatible data and header files, which can then be integrated directly into a system’s host processor. PARAMETER MEMORY The processing flow is outlined in Figure 52.
ADAU1381 APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS GROUNDING Each analog and digital power supply pin should be bypassed to its nearest appropriate ground pin with a single 100 nF capacitor. The connections to each side of the capacitor should be as short as possible, and the trace should stay on a single layer with no vias.
ADAU1381 CONTROL REGISTER MAP All registers except the PLL control register are 1-byte write and read registers. Table 27.
ADAU1381 CLOCK MANAGEMENT, INTERNAL REGULATOR, AND PLL CONTROL Register 16384 (0x4000), Clock Control The clock control register sets the clocking scheme for the ADAU1381. The system clock can be generated from either the PLL or directly from the MCKI (master clock input) pin. Additionally, the MCKO (master clock output) pin can be configured. Bits[6:5], MCKO Frequency These bits set the frequency to be output on MCKO as a multiple of the base sampling frequency (32×, 64×, 128×, or 256×).
ADAU1381 Register 16385 (0x4001), Regulator Control Bits[2:1], Regulator Output Level Bits[10:9], Input Divider These bits set the regulated voltage output for the digital core, DVDDOUT. After the initialization sequence has completed, the regulator output is set to 1.4 V. The recommended regulator output level when the device begins to process audio is 1.5 V. Therefore, this register should be set to 1.5 V when the sound engine is being configured.
ADAU1381 Table 32.
ADAU1381 Table 33. Fractional PLL Parameter Settings for fS = 44.1 kHz (fS = 44.1 kHz, Core Clock = 256 × 44.1 kHz, PLL Clock = 45.1584 MHz) MCLK Input (MHz) 12 13 14.4 19.2 19.68 19.8 Input Divider (X) 1 1 1 1 1 1 Integer (R) 3 3 3 2 2 2 Denominator (M) 625 8125 125 125 2035 1375 Numerator (N) 477 3849 17 44 302 386 Table 34. Fractional PLL Parameter Settings for fS = 48 kHz (fS = 48 kHz, Core Clock = 256 × 48 kHz, PLL Clock = 49.152 MHz) MCLK Input (MHz) 12 13 14.4 19.2 19.68 19.
ADAU1381 RECORD PATH CONFIGURATION Bit 3, Beep Input Mute Register 16392 (0x4008), Digital Microphone and Analog Beep Control This bit mutes the beep input. This register controls the digital microphone settings and the analog beep input gain. Bits[5:4], Digital Microphone Enable These bits control the enable function for the stereo digital microphones. The analog front end is powered down when using a digital microphone.
ADAU1381 Register 16393 (0x4009), Record Power Management Bits[6:5], Mixer Amplifier Boost This register manages the power consumption for the record path. In particular, the current distribution for the mixer boosts, ADC, front-end mixer, and PGAs can be set in one of four modes. The four modes of operation available that affect the performance of the device are normal operation, power saving, enhanced performance, and extreme power saving. Normal operation has a base current of 2.
ADAU1381 Register 16398 (0x400E), Record Gain Left PGA The record gain left PGA control register controls the left channel input PGA. This register configures the input for either differential or single-ended signals and sets the left channel input recording volume. input pin (LMICP) is disabled, and the complementary input of the PGA is switched to common mode. Bit 1, Record Path Left Mute This bit mutes the left channel input PGA.
ADAU1381 Register 16399 (0x400F), Record Gain Right PGA The record gain right PGA control register controls the right channel input PGA. This register configures the input for either differential or single-ended signals and sets the right channel input recording volume. input pin (RMICP) is disabled, and the complementary input of the PGA is switched to common mode. Bit 1, Record Path Right Mute This bit mutes the entire right channel input PGA.
ADAU1381 Register 16400 (0x4010), Microphone Bias Control and Beep Enable Bit 4, Beep Input Enable This bit enables the beep signal, which is input to the BEEP pin. Setting this bit to 0 mutes the beep signal for all output paths. Bit 2, Microphone Gain Provides two voltage bias options, 0.65 × AVDD1 and 0.90 × AVDD1. A higher bias contributes to a higher microphone gain. The maximum current that can be drawn from MICBIAS is 5 mA. Bit 0, Microphone Bias Enable This bit enables the MICBIAS output.
ADAU1381 SERIAL PORT CONFIGURATION Bits[2:1], Channels per Frame Register 16405 (0x4015), Serial Port Control 0 Bit 5, LRCLK Mode These bits set the number of channels contained in the data stream (see Figure 59). The possible choices are stereo (used in standard I2S signals), TDM 4 (a 4-channel time division multiplexed stream), or TDM 8 (an 8-channel time division multiplexed stream).
ADAU1381 BCLK POLARITY LRCLK BCLK SDATA LRCLK 08313-055 BCLK SDATA Figure 57. Serial Port BCLK Polarity LRCLK POLARITY LRCLK R L R L R 08313-056 L LRCLK Figure 58. Serial Port LRCLK Polarity 1/fLRCLK LRCLK 1 TDM 4 CHANNELS 2 1 TDM 8 CHANNELS 2 1 2 3 3 4 4 5 6 7 8 08313-057 STEREO CHANNELS Figure 59. Channels per Frame 1/fLRCLK LRCLK TDM 4 CHANNELS TDM 8 CHANNELS 1 1 2 3 4 FIRST PAIR SECOND PAIR THIRD PAIR FOURTH PAIR 2 3 4 5 Figure 60. TDM Channel Pairs Rev.
ADAU1381 Bit 2, MSB Position Register 16406 (0x4016), Serial Port Control 1 Bits[7:5], Number of Bit Clock Cycles per Frame These bits set the number of BCLK cycles contained in one LRCLK period. The frequency of BCLK is calculated as the number of bit clock cycles per frame times the sample rate of the serial port in hertz. Figure 61 and Figure 62 show examples of different settings for these bits.
ADAU1381 1/fLRCLK BCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 08313-059 LRCLK Figure 61. Example: 32 BCLK Cycles per Frame 1/fLRCLK 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Figure 62.
ADAU1381 1/fLRCLK LRCLK SERIAL DATA (DELAY BY 1) SERIAL DATA (DELAY BY 8) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 M L M M L M L M L L M 08313-064 BCLK SERIAL DATA (DELAY BY 0) L Figure 66.
ADAU1381 AUDIO CONVERTER CONFIGURATION Bit 4, DAC Oversampling Ratio Register 16407 (0x4017), Converter Control 0 Bits[6:5], On-Chip DAC Data Selection in TDM Mode This bit sets the oversampling ratio of the DAC relative to the audio sample rate. The higher rate yields slightly better audio quality but increases power consumption. These bits set the position of the DAC input channels on a TDM stream. In TDM 4 mode, valid settings are first pair or second pair.
ADAU1381 1/fLRCLK LRCLK RIGHT FIRST PAIR SECOND PAIR TDM 8 CHANNELS LEFT THIRD PAIR FOURTH PAIR RIGHT 08313-066 SECOND PAIR FIRST PAIR LEFT TDM 4 CHANNELS Figure 68. Example of Left Channel First, First Pair TDM Setting 1/fLRCLK LRCLK TDM 4 CHANNELS FIRST PAIR SECOND PAIR RIGHT TDM 8 CHANNELS RIGHT LEFT THIRD PAIR FOURTH PAIR LEFT 08313-067 SECOND PAIR FIRST PAIR Figure 69.
ADAU1381 Register 16408 (0x4018), Converter Control 1 Bits[1:0], On-Chip ADC Data Selection in TDM Mode with Register 16406 (0x4016), Serial Port Control 1, Bit 4, ADC channel position in TDM, to select where the data should appear in the TDM stream. These bits set the position of the ADC output channels on a TDM stream. In TDM 4 mode, valid settings are first pair or second pair. In TDM 8 mode, valid settings are first pair, second pair, third pair, or fourth pair.
ADAU1381 Bit 3, Digital Microphone Channel Swap Register 16409 (0x4019), ADC Control Bit 6, Invert Input Polarity This bit enables an optional polarity inverter in the ADC path, which is an amplifier with a gain of −1, representing a 180° phase shift. Bit 5, High-Pass Filter Select This bit allows the left and right channels of the digital microphone input to swap. Standard mode is the left channel on the rising edge and the right channel on the falling edge.
ADAU1381 Register 16410 (0x401A), Left ADC Attenuator Bits[7:0], Left ADC Digital Attenuator Register 16411 (0x401B), Right ADC Attenuator Bits[7:0], Right ADC Digital Attenuator These bits control a 256-step, logarithmically spaced volume control from 0 dB to −95.625 dB, in increments of 0.375 dB. When a new value is entered into this register, the volume control slews gradually to the new value, avoiding pops and clicks in the process. The slew ramp is logarithmic, incrementing 0.375 dB per audio frame.
ADAU1381 PLAYBACK PATH CONFIGURATION Register 16412 (0x401C), Playback Mixer Left Control Bit 5, Left DAC Mute This bit mutes the left DAC output. It does not have any slew and is updated immediately when the register write has been completed. This results in an abrupt cutoff of the audio output and should therefore be preceded by a soft mute in the sound engine or a slew mute using the DAC attenuator. Bits[4:1], Left Playback Beep Gain These bits set the gain of the beep signal in the left playback path.
ADAU1381 Register 16415 (0x401F), Playback Mono Mixer Control Bit 7, Left DAC Mute This bit mutes the left DAC output, but does not power down the DAC. Use of this bit does not result in power savings. Bit 6, Right DAC Mute This bit mutes the right DAC output, but does not power down the DAC. Use of this bit does not result in power savings. Bits[5:2], Mono Playback Beep Gain These bits set the gain of the beep output signal in mono mode.
ADAU1381 Register 16421 (0x4025), Left Line Output Mute Bit 1, Left Line Output Mute Register 16422 (0x4026), Right Line Output Mute Bit 1, Right Line Output Mute This bit mutes the left line output. It does not have any effect on the speaker outputs. This bit mutes the right line output. It does not have any effect on the speaker outputs. Table 51. Left Line Output Mute Register Bits [7:2] 1 0 Description Reserved Left line output mute (active low) 0: muted 1: unmuted Reserved Default 0 Table 52.
ADAU1381 Register 16423 (0x4027), Playback Speaker Output Control Bits[7:6], Speaker Output Gain Control Register 16424 (0x4028), Beep Zero-Crossing Detector Control Bits[4:3], Detector Timeout These bits control the gain of the speaker output. In general, this parameter should be tuned at a system level, set once during system initialization and not altered during operation of the system.
ADAU1381 Register 16425 (0x4029), Playback Power Management Bits[5:4], DAC Bias Control This register controls the unity current supplied to each functional block described. Within the functional blocks, the current can be multiplied. Normal operation has a base current of 2.5 μA, enhanced performance has a base current of 3 μA, power saving has a base current of 2 μA, and extreme power saving has a base current of 1.5 μA.
ADAU1381 Bit 5, Invert Input Polarity Register 16426 (0x402A), DAC Control Bits[7:6], Mono Mode These bits control the output mode of the DAC. Setting these bits to 00 outputs two distinct channels, left and right. Setting these bits to 01 outputs the left input channel on both the left and right outputs, and the right input channel is lost. Setting these bits to 10 outputs the right input channel on both the left and right outputs, and the left input channel is lost.
ADAU1381 Register 16427 (0x402B), Left DAC Attenuator Bits[7:0], Left DAC Digital Attenuator Register 16428 (0x402C), Right DAC Attenuator Bits[7:0], Right DAC Digital Attenuator These bits control a 256-step, logarithmically spaced volume control from 0 dB to −95.625 dB, in increments of 0.375 dB. When a new value is entered into this register, the volume control slews gradually to the new value, avoiding pops and clicks in the process. The slew ramp is logarithmic, incrementing 0.375 dB per audio frame.
ADAU1381 PAD CONFIGURATION Figure 71 shows a block diagram of the pad design for the GPIO/serial port and communications port pins.
ADAU1381 Bits[3:2], LRCLK Pad Pull-Up/Pull-Down Register 16429 (0x402D), Serial Port Pad Control 0 Bits[7:6], ADC_SDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[5:4], DAC_SDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ.
ADAU1381 Bit 1, LRCLK Pin Drive Strength Register 16430 (0x402E), Serial Port Pad Control 1 Bit 3, ADC_SDATA Pin Drive Strength This bit sets the drive strength of the ADC_SDATA pin. Low mode yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when IOVDD = 1.8 V. Bit 2, DAC_SDATA Pin Drive Strength This bit sets the drive strength of the DAC_SDATA pin. Low mode yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.
ADAU1381 Bits[3:2], SCL/CCLK Pad Pull-Up/Pull-Down Register 16431 (0x402F), Communication Port Pad Control 0 Bits[7:6], CDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[5:4], CLATCH Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ.
ADAU1381 Bit 1, SCL/CCLK Pin Drive Strength Register 16432 (0x4030), Communication Port Pad Control 1 Bit 3, CDATA Pin Drive Strength This bit sets the drive strength of the CDATA pin. Low mode yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when IOVDD = 1.8 V. Bit 2, CLATCH Pin Drive Strength This bit sets the drive strength of the CLATCH pin. Low mode yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.
ADAU1381 Bit 1, MCKO Pull-Up Enable Register 16433 (0x4031), MCKO Control Bit 2, MCKO Pin Drive Strength This bit sets the drive strength of the MCKO pin. Low mode yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when IOVDD = 1.8 V. This bit enables or disables a weak pull-up device on the pad. The effective resistance of the pull-up is nominally 240 kΩ.
ADAU1381 Register 16434 (0x4032), Dejitter Control Bits[7:0], Dejitter Window Size The dejitter control register not only allows the size of the dejitter window to be set, but also allows all dejitter circuits in the device to be activated or bypassed. Dejitter circuits protect against duplicate samples or skipped samples due to jitter from the serial ports in slave mode.
ADAU1381 DIGITAL SUBSYSTEM CONFIGURATION Bit 3, Serial Output Routing Register 16512 (0x4080), Digital Power-Down 0 Bit 7, ADC Engine Setting this bit to 0 disables the routing paths for the record signal path, which goes from the sound engine to the serial port output. Setting this bit to 0 disables the ADCs and the digital microphone inputs.
ADAU1381 Register 16513 (0x4081), Digital Power-Down 1 Bit 3, Output Precharge Bit 1, Digital Microphone The output precharge system allows the outputs to be biased before they are enabled and prevents pops or clicks from appearing on the output. This bit should be set to 1 at all times. Bit 0, DAC Engine Setting this bit to 0 disables the digital microphone input. Setting this bit to 0 disables the DACs.
ADAU1381 The GPIO pin can be set directly by the sound engine and therefore should be set as 1011 or 1100 (outputs set by the sound engine). In order for GPIO0 through GPIO3 to be used, they should be configured as 1001 or 1010 (outputs set by the I2C/SPI port). Register 16582 to Register 16586 (0x40C6 to 0x40CA), GPIO Pin Control Bits[3:0], GPIO Pin Function The GPIO pin control register sets the functionality of each GPIO pin as depicted in Table 68.
ADAU1381 Register 16617 and Register 16618 (0x40E9 and 0x40EA), Nonmodulo Register 16619 (0x40EB), Sound Engine Frame Rate Bits[3:0], Sound Engine Frame Rate These registers set the boundary for the nonmodulo RAM space used by the sound engine. An appropriate value is automatically loaded to this register during initialization. It should not be modified for any reason. These bits set the frequency of the frame start pulse, which is delivered to the sound engine to begin processing on each audio frame.
ADAU1381 Register 16626 (0x40F2), Serial Input Route Control Bits[3:0], Input Routing These bits select which serial data input channels are routed to the DACs (see Figure 72). Table 72.
ADAU1381 Register 16627 (0x40F3), Serial Output Route Control Bits[3:0], Output Routing These bits select where the ADC outputs are routed in the serial data stream (see Figure 72). Table 73. Serial Output Route Control Register Bits [7:4] [3:0] Default 0000 Lx = left side of Channel x; Rx = right side of Channel x. 1/fLRCLK LRCLK L0 STEREO CHANNELS L0 TDM 4 CHANNELS TDM 8 CHANNELS R0 L0 R0 R0 L1 L1 R1 L2 Figure 72. Serial Port Routing Control Rev.
ADAU1381 Register 16628 (0x40F4), Serial Data/GPIO Pin Configuration Bits[3:0], GPIO[0:3] Before going into standby mode, the following sequence must be performed: 1. The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1, then the GPIO[0:3] pins become GPIO interfaces to the sound engine. If these bits are set to 0, they remain LRCLK, BCLK, or serial port data pins, respectively. 2. 3.
ADAU1381 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 25 24 PIN 1 INDICATOR 4.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 12° MAX 17 16 SEATING PLANE 0.30 0.23 0.18 3.65 3.50 SQ 3.35 9 8 0.25 MIN 0.80 MAX 0.65 TYP 3.50 REF 0.05 MAX 0.02 NOM 1.00 0.85 0.80 1 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 100608-A TOP VIEW 0.
