SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL ADAU1761 FEATURES GENERAL DESCRIPTION SigmaDSP 28-/56-bit, 50 MIPS digital audio processor Fully programmable with SigmaStudio graphical tool 24-bit stereo audio ADC and DAC: >98 dB SNR Sampling rates from 8 kHz to 96 kHz Low power: 7 mW record, 7 mW playback, 48 kHz at 1.
ADAU1761 TABLE OF CONTENTS Features .............................................................................................. 1 Playback Signal Path ...................................................................... 35 Applications....................................................................................... 1 Output Signal Paths ................................................................... 35 General Description ...................................................................
ADAU1761 REVISION HISTORY 9/10—Rev. B to Rev. C Changes to Figure 1...........................................................................1 5/10—Rev. A to Rev. B Changes to Burst Mode Writing and Reading Section ..............38 Changes to Table 33 ........................................................................51 Added R67: Dejitter Control, 16,438 (0x4036) Section .............79 12/09—Rev. 0 to Rev. A Changes to Features Section ............................................................
ADAU1761 SPECIFICATIONS Supply voltage (AVDD) = 3.3 V, TA = 25°C, master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, CLOAD (digital output) = 20 pF, ILOAD (digital output) = 2 mA, VIH = 2 V, VIL = 0.8 V, unless otherwise noted. Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
ADAU1761 Parameter PSEUDO-DIFFERENTIAL PGA INPUT Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Volume Control Step Volume Control Range PGA Boost Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Common-Mode Rejection Ratio FULL DIFFERENTIAL PGA INPUT Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter (
ADAU1761 Parameter Interchannel Isolation Common-Mode Rejection Ratio MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.
ADAU1761 Parameter DAC TO HEADPHONE/EARPIECE OUTPUT Full-Scale Output Voltage (0 dB) Total Harmonic Distortion + Noise 16 Ω load 32 Ω load Power Supply Rejection Ratio Interchannel Isolation REFERENCE Common-Mode Reference Output Test Conditions/Comments PO = output power per channel Min Scales linearly with AVDD AVDD = 1.8 V AVDD = 3.3 V −4 dBFS AVDD = 1.8 V, PO = 6.4 mW AVDD = 3.3 V, PO = 21.1 mW AVDD = 1.8 V, PO = 3.8 mW AVDD = 3.3 V, PO = 10.
ADAU1761 TYPICAL CURRENT CONSUMPTION Master clock = 12.288 MHz, input sample rate = 48 kHz, input tone = 1 kHz, normal power management settings, ADC input @ −1 dBFS, DAC input @ 0 dBFS. For total power consumption, add the IOVDD current listed in Table 2. Table 3. Operating Voltage AVDD = IOVDD = 3.
ADAU1761 TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, integer PLL, input sample rate = 48 kHz, input tone = 1 kHz. Pseudo-differential input to ADCs, DACs to line output with 10 kΩ load. ADC input @ −1 dBFS, DAC input @ 0 dBFS. In Table 4, the mixer boost and power management conditions are set for MXBIAS[1:0], ADCBIAS[1:0], HPBIAS[1:0], and DACBIAS[1:0].
ADAU1761 DIGITAL FILTERS Table 5. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode All modes, typ @ 48 kHz Factor Min 0.4375 fS Max Unit 22.9844/fS 21 ±0.015 24 27 67 479 kHz dB kHz kHz dB μs 0.4535 fS 0.3646 fS 22 35 kHz kHz dB dB kHz kHz kHz kHz dB dB μs μs 0.5 fS 0.
ADAU1761 DIGITAL TIMING SPECIFICATIONS −40°C < TA < +85°C, IOVDD = 3.3 V ± 10%. Table 7. Digital Timing Parameter MASTER CLOCK tMP tMP tMP tMP SERIAL PORT tBIL tBIH tLIS tLIH tSIS tSIH tSODM SPI PORT fCCLK tCCPL tCCPH tCLS tCLH tCLPH tCDS tCDH tCOD I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tSCR tSCF tSDR tSDF tBFT DIGITAL MICROPHONE tDCF tDCR tDDV tDDH tMIN 74 37 24.7 18.5 Limit tMAX Unit Description 488 244 162.7 122 ns ns ns ns MCLK period, 256 × fS mode. MCLK period, 512 × fS mode.
ADAU1761 DIGITAL TIMING DIAGRAMS tLIH tBIH BCLK tBIL tLIS LRCLK tSIS DAC_SDATA LEFT-JUSTIFIED MODE MSB MSB – 1 tSIH tSIS DAC_SDATA I2S MODE MSB tSIH tSIS tSIS DAC_SDATA RIGHT-JUSTIFIED MODE LSB MSB tSIH tSIH 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 07680-002 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 2.
ADAU1761 tCLS tCLH tCLPH tCCPL tCCPH CLATCH CCLK CDATA tCDH tCDS COUT 07680-004 tCOD Figure 4. SPI Port Timing tDS tSCH tSCH SDA tSCLH SCL tSCLL tSCS tSCF tBFT Figure 5. I2C Port Timing tDCF tDCR CLK DATA1/ DATA2 DATA1 DATA2 tDDH tDDV tDDV DATA1 DATA2 Figure 6. Digital Microphone Timing Rev.
ADAU1761 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Power Supply (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range Storage Temperature Range Rating −0.3 V to +3.65 V ±20 mA −0.3 V to AVDD + 0.3 V −0.3 V to IOVDD + 0.3 V −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
ADAU1761 32 31 30 29 28 27 26 25 SCL/CCLK SDA/COUT ADDR1/CDATA LRCLK/GPIO3 BCLK/GPIO2 DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 DGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADAU1761 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 DVDDOUT AVDD AGND MONOOUT LHP RHP LOUTP LOUTN NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1761 GROUNDS.
ADAU1761 Pin No. 19 20 21 Mnemonic RHP LHP MONOOUT Type 1 A_OUT A_OUT A_OUT 22 AGND PWR 23 AVDD PWR 24 DVDDOUT PWR 25 DGND PWR 26 ADC_SDATA/GPIO1 D_IO 27 DAC_SDATA/GPIO0 D_IO 28 BCLK/GPIO2 D_IO 29 LRCLK/GPIO3 D_IO 30 ADDR1/CDATA D_IN 31 SDA/COUT D_IO 32 SCL/CCLK D_IN EP Exposed Pad 1 Description Right Headphone Output. Biased at AVDD/2. Left Headphone Output. Biased at AVDD/2. Mono Output or Virtual Ground for Capless Headphone.
ADAU1761 28 –30 26 –35 24 –40 22 –45 20 –50 –55 16 14 12 10 –65 –70 –75 –80 8 –85 6 –90 4 –95 2 –100 0 –60 –50 –40 –30 –20 –10 0 DIGITAL 1kHz INPUT SIGNAL (dBFS) –105 –60 –50 –40 –30 –20 –10 0 DIGITAL 1kHz INPUT SIGNAL (dBFS) Figure 8. Headphone Amplifier Power vs. Input Level, 16 Ω Load Figure 11. Headphone Amplifier THD + N vs.
0.10 –10 0.08 –20 0.06 –30 0.04 –40 –50 –60 –70 0.02 0 –0.02 –0.04 –80 –0.06 –90 –0.08 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (NORMALIZED TO fS) –0.10 0 Figure 14. ADC Decimation Filter, 128× Oversampling, Normalized to fS 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY (NORMALIZED TO fS) 07680-011 MAGNITUDE (dBFS) 0 07680-010 MAGNITUDE (dBFS) ADAU1761 Figure 17.
0.05 –10 0.04 –20 0.03 –30 0.02 –40 –50 –60 –70 0.01 0 –0.01 –0.02 –80 –0.03 –90 –0.04 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (NORMALIZED TO fS) –0.05 Figure 20. DAC Interpolation Filter, 128× Oversampling, Normalized to fS 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY (NORMALIZED TO fS) 07680-017 MAGNITUDE (dBFS) 0 07680-016 MAGNITUDE (dBFS) ADAU1761 Figure 23.
ADAU1761 SYSTEM BLOCK DIAGRAMS FROM VOLTAGE REGULATOR (1.8V TO 3.3V) 10µF + 0.1µF 10µF 10µF + + 0.1µF 0.1µF 0.1µF 1.2nH THE INPUT CAPACITOR VALUE DEPENDS ON THE INPUT IMPEDANCE, WHICH VARIES WITH THE VOLUME SETTING. DVDDOUT IOVDD AVDD 9.
ADAU1761 FROM VOLTAGE REGULATOR (1.8V TO 3.3V) 10µF + 0.1µF 10µF 10µF + + 0.1µF 0.1µF 0.1µF 1.2nH THE INPUT CAPACITOR VALUE DEPENDS ON THE INPUT IMPEDANCE, WHICH VARIES WITH THE VOLUME SETTING. DVDDOUT IOVDD AVDD 9.
ADAU1761 FROM VOLTAGE REGULATOR (1.8V TO 3.3V) 10µF + 0.1µF 10µF 10µF + + 0.1µF 0.1µF 0.1µF 1.2nH DVDDOUT IOVDD AVDD MICBIAS RHP CM LHP LINP 10µF LINN DIGITAL DATA MICROPHONE L/R SELECT 2.5V TO 5.0V MONOOUT CLK 0.1µF CAPLESS HEADPHONE OUTPUT AVDD BCLK VDD 9.
ADAU1761 THEORY OF OPERATION The ADAU1761 is a low power audio codec with an integrated stream-oriented DSP core, making it an all-in-one package that offers high quality audio, low power, small size, and many advanced features. The stereo ADC and stereo DAC each have an SNR of at least +98 dB and a THD + N of at least −90 dB. The serial data port is compatible with I2S, left-justified, rightjustified, and TDM modes for interfacing to digital audio data. The operating voltage range is 1.8 V to 3.
ADAU1761 STARTUP, INITIALIZATION, AND POWER This section describes the procedure for properly starting up the ADAU1761. The following sequence provides a high level approach to the proper initiation of the system. 1. 2. 3. 4. POWER REDUCTION MODES Sections of the ADAU1761 chip can be turned on and off as needed to reduce power consumption. These include the ADCs, the DACs, the PLL, and the DSP core. Apply power to the ADAU1761. Lock the PLL to the input clock (if using the PLL). Enable the core clock.
ADAU1761 Case 2: PLL Is Used The core clock to the entire chip is off during the PLL lock acquisition period. The user can poll the lock bit to determine when the PLL has locked. After lock is acquired, the ADAU1761 can be started by asserting the core clock enable bit (COREN) in Register R0 (clock control register, Address 0x4000). This bit enables the core clock to all the internal blocks of the ADAU1761.
ADAU1761 CLOCKING AND SAMPLING RATES R57: DSP SAMPLING RATE SETTING DSPSR[3:0] fS/0.5, 1, 1.5, 2, 3, 4, 6 R1: PLL CONTROL REGISTER MCLK ÷X R0: CLOCK CONTROL REGISTER × (R + N/M) CLKSRC INFREQ[1:0] 256 × fS, 512 × fS, 768 × fS, 1024 × fS ADCs R17: CONVERTER SAMPLING RATE CORE CLOCK DACs CONVSR[2:0] fS/0.5, 1, 1.5, 2, 3, 4, 6 R64: SERIAL PORT SAMPLING RATE ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 DAC_SDATA/GPIO0 SERIAL DATA INPUT/ OUTPUT PORT 07680-020 SPSR[2:0] fS/0.5, 1, 1.
ADAU1761 SAMPLING RATES PLL The ADCs, DACs, and serial port share a common sampling rate that is set in Register R17 (Converter Control 0 register, Address 0x4017). The CONVSR[2:0] bits set the sampling rate as a ratio of the base sampling frequency.
ADAU1761 Bits [10:9] Bit Name X[1:0] 8 Type 1 Lock 0 PLLEN Description PLL input clock divider 00: X = 1 (default) 01: X = 2 10: X = 3 11: X = 4 PLL operation mode 0: Integer (default) 1: Fractional PLL lock (read-only bit) 0: PLL unlocked (default) 1: PLL locked PLL enable 0: PLL disabled (default) 1: PLL enabled Table 16. Fractional PLL Parameter Settings for fS = 44.1 kHz (PLL Output = 45.1584 MHz = 1024 × fS) MCLK Input (MHz) 8 12 13 14.4 19.2 19.68 19.
ADAU1761 RECORD SIGNAL PATH MICIN LEFT DIGITAL MICROPHONE INTERFACE JACKDET/MICIN MICIN RIGHT LINNG[2:0] MIXER 1 (LEFT RECORD MIXER) –12dB TO +6dB PGA LDBOOST[1:0] LINN –12dB TO +35.
ADAU1761 Analog Microphone Inputs Analog Line Inputs For microphone inputs, configure the part in either stereo pseudo-differential mode or stereo full differential mode. Line input signals can be accepted by any analog input.
ADAU1761 Digital Microphone Input Microphone Bias When using a digital microphone connected to the JACKDET/ MICIN pin, the JDFUNC[1:0] bits in Register R2 (Address 0x4008) must be set to 10 to enable the microphone input and disable the jack detection function. The ADAU1761 must operate in master mode and source BCLK to the input clock of the digital microphone. The DSPRUN bit must also be asserted in Register R62 (DSP run register, Address 0x40F6) for digital microphone operation.
ADAU1761 AUTOMATIC LEVEL CONTROL (ALC) • The ADAU1761 contains a hardware automatic level control (ALC). The ALC is designed to continuously adjust the PGA gain to keep the recording volume constant as the input level varies. For optimal noise performance, the ALC uses the analog PGA to adjust the gain instead of using a digital method. This ensures that the ADC noise is not amplified at low signal levels. Extremely small gain step sizes are used to ensure high audio quality during gain changes.
ADAU1761 the threshold for 250 ms before the noise gate operates. Hysteresis is used so that the threshold for coming out of the mute state is 6 dB higher than the threshold for going into the mute state. There are four operating modes for the noise gate. INPUT Noise Gate Mode 0 (see Figure 40) is selected by setting the NGTYP[1:0] bits to 00. In this mode, the current state of the PGA gain is held at its current state when the noise gate logic is activated.
ADAU1761 Noise Gate Mode 3 (see Figure 43) is selected by setting the NGTYP[1:0] bits to 11. This mode is the same as Mode 2 except that at the end of the PGA fade gain interval, a digital mute is performed. In general, this mode is the best-sounding mode, because the audible effect of the digital hard mute is reduced by the fact that the gain has already faded to a low level before the mute occurs. Noise Gate Mode 2 (see Figure 42) is selected by setting the NGTYP[1:0] bits to 10.
ADAU1761 PLAYBACK SIGNAL PATH MX3G1[3:0] LEFT INPUT MIXER –15dB TO +6dB MX3G2[3:0] RIGHT INPUT MIXER MIXER 3 (LEFT PLAYBACK MIXER) –15dB TO +6dB MX3AUXG[3:0] LAUX LHPVOL[5:0] –15dB TO +6dB –57dB TO +6dB MIXER 5 (LEFT L/R PLAYBACK MIXER) LEFT DAC LHP LOUTVOL[5:0] MX3LM –57dB TO +6dB LOUTP MX5G3[1:0] RIGHT DAC MX3RM –1 MX6G3[1:0] LOUTN MONOVOL[5:0] MX7[1:0] MIXER 7 (MONO MIXER) MONOOUT –57dB TO +6dB –1 MX4G1[3:0] LEFT INPUT MIXER –15dB TO +6dB MX5G4[1:0] MX4G2[3:0] RIGHT INPUT MIXER
ADAU1761 HEADPHONE OUTPUT Headphone Output Power-Up/Power-Down Sequencing The LHP and RHP pins can be driven by either a line output driver or a headphone driver by setting the HPMODE bit in Register R30 (playback headphone right volume control register, Address 0x4024). The headphone outputs can drive a load of at least 16 Ω. To prevent pops when turning on the headphone outputs, the user must wait at least 4 ms to unmute these outputs after enabling the headphone output with the HPMODE bit.
ADAU1761 Jack Detection LINE OUTPUTS When the JACKDET/MICIN pin is set to the jack detect function, a flag on this pin can be used to mute the line outputs when headphones are plugged into the jack. This pin can be configured in Register R2 (digital microphone/jack detection control register, Address 0x4008). The JDFUNC[1:0] bits set the functionality of the JACKDET/MICIN pin. The line output pins (LOUTP, LOUTN, ROUTP, and ROUTN) can be used to drive both differential and single-ended loads.
ADAU1761 CONTROL PORTS The ADAU1761 can operate in one of two control modes: • • 2 I C control SPI control The ADAU1761 has both a 4-wire SPI control port and a 2-wire I2C bus control port. Both ports can be used to set the registers. The part defaults to I2C mode, but it can be put into SPI control mode by pulling the CLATCH pin low three times. The control port is capable of full read/write operation for all addressable registers.
ADAU1761 the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADAU1761 does not issue an acknowledge and returns to the idle condition. The R/W bit determines the direction of the data.
ADAU1761 I2C Read and Write Operations This causes the ADAU1761 SDA to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU1761. Figure 51 shows the format of a single-word write operation. Every ninth clock pulse, the ADAU1761 issues an acknowledge by pulling SDA low. Figure 54 shows the format of a burst mode read sequence. This figure shows an example of a read from sequential single-byte registers.
ADAU1761 SPI PORT Chip Address R/W 2 By default, the ADAU1761 is in I C mode, but it can be put into SPI control mode by pulling CLATCH low three times. This is done by performing three dummy writes to the SPI port (the ADAU1761 does not acknowledge these three writes). Beginning with the fourth SPI write, data can be written to or read from the IC. The ADAU1761 can be taken out of SPI mode only by a full reset initiated by power-cycling the IC.
ADAU1761 SERIAL DATA INPUT/OUTPUT PORTS If the PLL of the ADAU1761 is not used, the serial data clocks must be synchronous with the ADAU1761 master clock input. The LRCLK and BCLK pins are used to clock both the serial input and output ports. The ADAU1761 can be set as the master or the slave in a system. Because there is only one set of serial data clocks, the input and output ports must always be both master or both slave.
ADAU1761 LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK LSB MSB LSB MSB 07680-040 SDATA 1/fS 2 Figure 58. I S Mode—16 Bits to 24 Bits per Channel MSB LSB MSB LSB 07680-041 SDATA RIGHT CHANNEL LEFT CHANNEL LRCLK BCLK 1/fS Figure 59. Left-Justified Mode—16 Bits to 24 Bits per Channel RIGHT CHANNEL SDATA MSB LSB MSB LSB 07680-042 LEFT CHANNEL LRCLK BCLK 1/fS Figure 60.
ADAU1761 APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS GROUNDING Each analog and digital power supply pin should be bypassed to its nearest appropriate ground pin with a single 100 nF capacitor. The connections to each side of the capacitor should be as short as possible, and the trace should stay on a single layer with no vias.
ADAU1761 DSP CORE SIGNAL PROCESSING PROGRAM COUNTER The ADAU1761 is designed to provide all audio signal processing functions commonly used in stereo or mono low power record and playback systems. The signal processing flow is designed using the SigmaStudio software, which allows graphical entry and real-time control of all signal processing functions. The execution of instructions in the core is governed by a program counter, which sequentially steps through the addresses of the program RAM.
ADAU1761 NUMERIC FORMATS DSP systems commonly use a standard numeric format. Fractional numeric systems are specified by an A.B format, where A is the number of bits to the left of the decimal point and B is the number of bits to the right of the decimal point. The ADAU1761 uses numeric format 5.23 for both the parameter and data values. Numeric Format 5.23 The serial port accepts up to 24 bits on the input and is signextended to the full 28 bits of the DSP core.
ADAU1761 PROGRAM RAM, PARAMETER RAM, AND DATA RAM Table 26. RAM Map and Read/Write Modes Memory Parameter RAM Program RAM Size 1024 × 32 1024 × 40 Address Range 0 to 1023 (0x0000 to 0x03FF) 2048 to 3071 (0x0800 to 0x0BFF) Table 26 shows the RAM map (the ADAU1761 register map is provided in the Control Registers section). The address space encompasses a set of registers and three RAMs: program, parameter, and data.
ADAU1761 Table 27. Parameter RAM Read/Write Format (Single Address) Byte 0 chip_adr[6:0], R/W Byte 1 param_adr[15:8] Byte 2 param_adr[7:0] Byte 3 0000, param[27:24] Bytes[4:6] param[23:0] Table 28. Parameter RAM Block Read/Write Format (Burst Mode) Byte 0 chip_adr[6:0], R/W Byte 1 param_adr[15:8] Byte 2 param_adr[7:0] Byte 3 0000, param[27:24] Bytes[4:6] param[23:0] <—param_adr—> Bytes[7:10] Bytes[11:14] param_adr + 1 param_adr + 2 Table 29.
ADAU1761 SOFTWARE SLEW Because algorithms that use software slew generally require more RAM than their nonslew equivalents, they should be used only in situations where a parameter will change during operation of the device. Figure 70 shows an example of volume slew applied to a sine wave. The target value takes an additional space in parameter RAM, and the current value of the parameter is updated in the nonmodulo section of data RAM.
ADAU1761 GENERAL-PURPOSE INPUT/OUTPUT The serial data input/output pins (Pin 26 to Pin 29) are shared with the general-purpose input/output function. Each of these four pins can be set to only one of these functions. The function of these pins is set in the serial data/GPIO pin configuration register (Register R60, Address 0x40F4). The GPIOx pins can be used as inputs or outputs. These pins are readable and can be set through the control port or directly by the SigmaDSP core.
ADAU1761 CONTROL REGISTERS Table 33.
ADAU1761 Reg R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 Address 0x40C4 0x40C6 0x40C7 0x40C8 0x40C9 0x40D0 0x40D1 0x40D2 0x40D3 0x40D4 0x40EB R58 0x40F2 R59 0x40F3 R60 0x40F4 R61 R62 R63 R64 0x40F5 0x40F6 0x40F7 0x40F8 R65 R66 0x40F9 0x40FA Name CRC enable GPIO0 pin control GPIO1 pin control GPIO2 pin control GPIO3 pin control Watchdog enable Watchdog value Watchdog error DSP sampling rate setting Serial input route control Serial output route control Serial data/GPIO pin configuration DSP enab
ADAU1761 R1: PLL Control, 16,386 (0x4002) Byte 0 1 2 3 4 5 Bit 7 Bit 6 Reserved Bit 5 Bit 4 Bit 3 M[15:8] M[7:0] N[15:8] N[7:0] R[3:0] Reserved Bit 2 Bit 1 X[1:0] Lock Bit 0 Type PLLEN Table 35. PLL Control Register Byte 0 1 Bits [7:0] [7:0] Bit Name M[15:8] M[7:0] 2 3 [7:0] [7:0] N[15:8] N[7:0] 4 [6:3] R[3:0] 4 [2:1] X[1:0] 4 0 Type 5 1 Lock 5 0 PLLEN Description PLL denominator MSB. This value is concatenated with M[7:0] to make up a 16-bit number. PLL denominator LSB.
ADAU1761 R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008) Bit 7 Bit 6 JDDB[1:0] Bit 5 Bit 4 JDFUNC[1:0] Bit 3 Bit 2 Reserved Bit 1 Bit 0 JDPOL Table 36. Digital Microphone/Jack Detection Control Register Bits [7:6] Bit Name JDDB[1:0] [5:4] JDFUNC[1:0] 0 JDPOL Description Jack detect debounce time. Setting Debounce Time 00 5 ms (default) 01 10 ms 10 20 ms 11 40 ms JACKDET/MICIN pin function.
ADAU1761 R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A) This register controls the gain of single-ended inputs for the left channel record path. The left channel record mixer is referred to as Mixer 1. Bit 7 Reserved Bit 6 Bit 5 LINPG[2:0] Bit 4 Bit 3 Bit 2 LINNG[2:0] Table 38. Record Mixer Left (Mixer 1) Control 0 Register Bits [6:4] Bit Name LINPG[2:0] [3:1] LINNG[2:0] 0 MX1EN Description Gain for a left channel single-ended input from the LINP pin, input to Mixer 1.
ADAU1761 R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B) This register controls the gain boost of the left channel differential PGA input and the gain for the left channel auxiliary input in the record path. The left channel record mixer is referred to as Mixer 1. Bit 7 Bit 6 Reserved Bit 5 Bit 4 Bit 3 LDBOOST[1:0] Bit 2 Bit 1 MX1AUXG[2:0] Bit 0 Table 39.
ADAU1761 R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C) This register controls the gain of single-ended inputs for the right channel record path. The right channel record mixer is referred to as Mixer 2. Bit 7 Reserved Bit 6 Bit 5 RINPG[2:0] Bit 4 Bit 3 Bit 2 RINNG[2:0] Bit 1 Table 40. Record Mixer Right (Mixer 2) Control 0 Register Bits [6:4] Bit Name RINPG[2:0] [3:1] RINNG[2:0] 0 MX2EN Description Gain for a right channel single-ended input from the RINP pin, input to Mixer 2.
ADAU1761 R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D) This register controls the gain boost of the right channel differential PGA input and the gain for the right channel auxiliary input in the record path. The right channel record mixer is referred to as Mixer 2. Bit 7 Bit 6 Reserved Bit 5 Bit 4 Bit 3 RDBOOST[1:0] Bit 2 Bit 1 MX2AUXG[2:0] Bit 0 Table 41.
ADAU1761 R9: Right Differential Input Volume Control, 16,399 (0x400F) This register enables the differential path and sets the volume control for the right differential PGA input. Bit 7 Bit 6 Bit 5 Bit 4 RDVOL[5:0] Bit 3 Bit 2 Bit 1 RDMUTE Bit 0 RDEN Table 43. Right Differential Input Volume Control Register Bits [7:2] Bit Name RDVOL[5:0] 1 RDMUTE 0 RDEN Description Right channel differential PGA input volume control.
ADAU1761 R11: ALC Control 0, 16,401 (0x4011) Bit 7 Bit 6 PGASLEW[1:0] Bit 5 Bit 4 ALCMAX[2:0] Bit 3 Bit 2 Bit 1 ALCSEL[2:0] Bit 0 Table 45. ALC Control 0 Register Bits [7:6] Bit Name PGASLEW[1:0] [5:3] ALCMAX[2:0] [2:0] ALCSEL[2:0] Description PGA volume slew time when the ALC is off.
ADAU1761 R12: ALC Control 1, 16,402 (0x4012) Bit 7 Bit 6 Bit 5 ALCHOLD[3:0] Bit 4 Bit 3 Bit 2 Bit 1 ALCTARG[3:0] Bit 0 Table 46. ALC Control 1 Register Bits [7:4] Bit Name ALCHOLD[3:0] [3:0] ALCTARG[3:0] Description ALC hold time. The ALC hold time is the amount of time that the ALC waits after a decrease in input level before increasing the gain to achieve the target level. The recommended minimum setting is 21 ms (0011) to prevent distortion of low frequency signals.
ADAU1761 R13: ALC Control 2, 16,403 (0x4013) Bit 7 Bit 6 Bit 5 ALCATCK[3:0] Bit 4 Bit 3 Bit 2 Bit 1 ALCDEC[3:0] Bit 0 Table 47. ALC Control 2 Register Bits [7:4] Bit Name ALCATCK[3:0] [3:0] ALCDEC[3:0] Description ALC attack time. The attack time sets how fast the ALC starts attenuating after an increase in input level above the target. A typical setting for music recording is 384 ms, and a typical setting for voice recording is 24 ms.
ADAU1761 R14: ALC Control 3, 16,404 (0x4014) Bit 7 Bit 6 NGTYP[1:0] Bit 5 NGEN Bit 4 Bit 3 Bit 2 NGTHR[4:0] Bit 1 Bit 0 Table 48. ALC Control 3 Register Bits [7:6] Bit Name NGTYP[1:0] 5 NGEN [4:0] NGTHR[4:0] Description Noise gate type. When the input signal falls below the threshold for 250 ms, the noise gate can hold a constant PGA gain, mute the ADC output, fade the PGA gain to the minimum gain value, or fade then mute.
ADAU1761 R16: Serial Port Control 1, 16,406 (0x4016) Bit 7 Bit 6 BPF[2:0] Bit 5 Bit 4 ADTDM Bit 3 DATDM Table 50. Serial Port Control 1 Register Bits [7:5] Bit Name BPF[2:0] 4 ADTDM 3 DATDM 2 MSBP [1:0] LRDEL[1:0] Description Number of bit clock cycles per LRCLK audio frame. Setting Bit Clock Cycles 000 64 (default) 001 Reserved 010 48 011 128 100 256 Reserved 101 110 Reserved 111 Reserved ADC serial audio data channel position in TDM mode. 0 = left first (default). 1 = right first.
ADAU1761 R17: Converter Control 0, 16,407 (0x4017) Bit 7 Reserved Bit 6 Bit 5 DAPAIR[1:0] Bit 4 DAOSR Bit 3 ADOSR Bit 2 Bit 1 CONVSR[2:0] Bit 0 Table 51. Converter Control 0 Register Bits [6:5] Bit Name DAPAIR[1:0] 4 DAOSR 3 ADOSR [2:0] CONVSR[2:0] Description On-chip DAC serial data selection in TDM 4 or TDM 8 mode. Setting Pair 00 First pair (default) 01 Second pair 10 Third pair 11 Fourth pair DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
ADAU1761 R19: ADC Control, 16,409 (0x4019) Bit 7 Reserved Bit 6 ADCPOL Bit 5 HPF Bit 4 DMPOL Bit 3 DMSW Bit 2 INSEL Bit 1 Bit 0 ADCEN[1:0] Table 53. ADC Control Register Bits 6 Bit Name ADCPOL 5 HPF 4 DMPOL 3 DMSW 2 INSEL [1:0] ADCEN[1:0] Description Invert input polarity. 0 = normal (default). 1 = inverted. ADC high-pass filter select. At 48 kHz, f3dB = 2 Hz. 0 = off (default). 1 = on. Digital microphone data polarity swap. 0 = invert polarity. 1 = normal (default).
ADAU1761 R21: Right Input Digital Volume, 16,411 (0x401B) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RADVOL[7:0] Bit 2 Bit 1 Bit 0 Table 55. Right Input Digital Volume Register Bits [7:0] Bit Name RADVOL[7:0] Description Controls the digital volume attenuation for right channel inputs from either the right ADC or the right digital microphone input. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 94 for a complete list of the volume settings.
ADAU1761 R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D) Bit 7 Bit 6 Bit 5 MX3G2[3:0] Bit 4 Bit 3 Bit 2 Bit 1 MX3G1[3:0] Bit 0 Table 57. Playback Mixer Left (Mixer 3) Control 1 Register Bits [7:4] Bit Name MX3G2[3:0] [3:0] MX3G1[3:0] Description Bypass gain control. The signal from the right channel record mixer (Mixer 2) bypasses the converters and gain can be applied before the left playback mixer (Mixer 3).
ADAU1761 R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E) Bit 7 Reserved Bit 6 MX4RM Bit 5 MX4LM Bit 4 Bit 3 Bit 2 MX4AUXG[3:0] Bit 1 Bit 0 MX4EN Table 58. Playback Mixer Right (Mixer 4) Control 0 Register Bits 6 Bit Name MX4RM 5 MX4LM [4:1] MX4AUXG[3:0] 0 MX4EN Description Mixer input mute. Mutes the right DAC input to the right channel playback mixer (Mixer 4). 0 = muted (default). 1 = unmuted. Mixer input mute.
ADAU1761 R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F) Bit 7 Bit 6 Bit 5 MX4G2[3:0] Bit 4 Bit 3 Bit 2 Bit 1 MX4G1[3:0] Bit 0 Table 59. Playback Mixer Right (Mixer 4) Control 1 Register Bits [7:4] Bit Name MX4G2[3:0] [3:0] MX4G1[3:0] Description Bypass gain control. The signal from the right channel record mixer (Mixer 2) bypasses the converters and gain can be applied before the right playback mixer (Mixer 4).
ADAU1761 R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020) Bit 7 Bit 6 Reserved Bit 5 Bit 4 Bit 3 MX5G4[1:0] Bit 2 Bit 1 MX5G3[1:0] Bit 0 MX5EN Table 60. Playback L/R Mixer Left (Mixer 5) Line Output Control Register Bits [4:3] Bit Name MX5G4[1:0] [2:1] MX5G3[1:0] 0 MX5EN Description Mixer input gain boost. The signal from the right channel playback mixer (Mixer 4) can be enabled and boosted in the playback L/R mixer left (Mixer 5).
ADAU1761 R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022) Bit 7 Bit 6 Bit 5 Reserved Bit 4 Bit 3 Bit 2 Bit 1 MX7[1:0] Bit 0 MX7EN Table 62. Playback L/R Mixer Mono Output (Mixer 7) Control Register Bits [2:1] Bit Name MX7[1:0] 0 MX7EN Description L/R mono playback mixer (Mixer 7). Mixes the left and right playback mixers (Mixer 3 and Mixer 4) with either a 0 dB or 6 dB gain boost.
ADAU1761 R30: Playback Headphone Right Volume Control, 16,420 (0x4024) Bit 7 Bit 6 Bit 5 Bit 4 RHPVOL[5:0] Bit 3 Bit 2 Bit 1 RHPM Bit 0 HPMODE Table 64. Playback Headphone Right Volume Control Register Bits [7:2] Bit Name RHPVOL[5:0] 1 RHPM 0 HPMODE Description Headphone volume control for right channel, RHP output. Each 1-bit step corresponds to a 1 dB increase in volume. See Table 95 for a complete list of the volume settings.
ADAU1761 R32: Playback Line Output Right Volume Control, 16,422 (0x4026) Bit 7 Bit 6 Bit 5 Bit 4 ROUTVOL[5:0] Bit 3 Bit 2 Bit 1 ROUTM Bit 0 ROMODE Table 66. Playback Line Output Right Volume Control Register Bits [7:2] Bit Name ROUTVOL[5:0] 1 ROUTM 0 ROMODE Description Line output volume control for right channel, ROUTN and ROUTP outputs. Each 1-bit step corresponds to a 1 dB increase in volume. See Table 95 for a complete list of the volume settings.
ADAU1761 R34: Playback Pop/Click Suppression, 16,424 (0x4028) Bit 7 Bit 6 Reserved Bit 5 Bit 4 POPMODE Bit 3 POPLESS Bit 2 Bit 1 ASLEW[1:0] Bit 0 Reserved Table 68. Playback Pop/Click Suppression Register Bits 4 Bit Name POPMODE 3 POPLESS [2:1] ASLEW[1:0] Description Pop suppression circuit power saving mode. The pop suppression circuits charge faster in normal operation; however, after they are charged, they can be put into low power operation. 0 = normal (default). 1 = low power.
ADAU1761 R36: DAC Control 0, 16,426 (0x402A) Bit 7 Bit 6 DACMONO[1:0] Bit 5 DACPOL Bit 4 Bit 3 Reserved Bit 2 DEMPH Bit 1 Bit 0 DACEN[1:0] Table 70. DAC Control 0 Register Bits [7:6] Bit Name DACMONO[1:0] 5 DACPOL 2 DEMPH [1:0] DACEN[1:0] Description DAC mono mode. The DAC channels can be set to mono mode within the DAC and output on the left channel, the right channel, or both channels.
ADAU1761 R38: DAC Control 2, 16,428 (0x402C) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RDAVOL[7:0] Bit 2 Bit 1 Bit 0 Table 72. DAC Control 2 Register Bits [7:0] Bit Name RDAVOL[7:0] Description Controls the digital volume attenuation for right channel inputs from the right DAC. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 94 for a complete list of the volume settings. Setting Volume Attenuation 00000000 0 dB (default) 00000001 −0.375 dB 00000010 −0.75 dB … … 11111110 −95.
ADAU1761 R40: Control Port Pad Control 0, 16,431 (0x402F) The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the control port signals to a defined state when the signal source becomes three-state. Bit 7 Bit 6 CDATP[1:0] Bit 5 Bit 4 CLCHP[1:0] Bit 3 Bit 2 SCLP[1:0] Bit 1 Bit 0 SDAP[1:0] Table 74.
ADAU1761 R42: Jack Detect Pin Control, 16,433 (0x4031) With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively. With IOVDD set to 1.8 V, the low and high drive strengths are approximately 0.8 mA and 1.7 mA, respectively. The optional pull-up/ pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the input signals to a defined state when the signal source becomes three-state.
ADAU1761 R43 to R47: Cyclic Redundancy Check Registers, 16,576 to 16,580 (0x40C0 to 0x40C4) The cyclic redundancy check (CRC) constantly checks the validity of the program RAM contents. SigmaStudio generates a 32-bit hash sum, which must be written to four consecutive read-only 8-bit register locations. CRC must then be enabled. Every 1024 frames (21 ms at 48 kHz), the IC generates its own 32-bit code and compares it to the one stored in these registers.
ADAU1761 R48 to R51: GPIO Pin Control, 16,582 to 16,585 (0x40C6 to 0x40C9) The GPIO pin control register sets the functionality of each GPIO pin as shown in Table 79. The GPIO functions use the same pins as the serial port and must be enabled in the serial data/GPIO pin configuration register (Address 0x40F4). When the GPIO pins are set to I2C/SPI port control mode, the pins are set through writes to memory locations described in Table 32. The value of the optional internal pull-up is nominally 250 kΩ.
ADAU1761 R52 to R56: Watchdog Registers, 16,592 to 16,596 (0x40D0 to 0x40D4) A program counter watchdog is used when the core does block processing (which can span several samples). The watchdog flags an error if the program counter reaches a specific 24-bit value (ranging from 0x000000 to 0xFFFFFF) that is set in the register map. This value consists of three consecutive 8-bit register locations. The error flag sends a high signal to one of the GPIO pins.
ADAU1761 R58: Serial Input Route Control, 16,626 (0x40F2) Bit 7 Bit 6 Bit 5 Reserved Bit 4 Bit 3 Bit 2 Bit 1 SINRT[3:0] Bit 0 Table 83. Serial Input Route Control Register Bits [3:0] Bit Name SINRT[3:0] Description Serial data input routing. This register sets the input where the DACs receive serial data. This location can be from the DSP or from any TDM slot on the serial port.
ADAU1761 R60: Serial Data/GPIO Pin Configuration, 16,628 (0x40F4) The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1, these pins are configured as GPIO interfaces to the SigmaDSP. If these bits are set to 0, they are configured as serial data I/O port pins. Bit 7 Bit 6 Bit 5 Reserved Bit 4 Bit 3 LRGP3 Bit 2 BGP2 Bit 1 SDOGP1 Bit 0 SDIGP0 Bit 2 Bit 1 Bit 0 DSPEN Table 85.
ADAU1761 R63: DSP Slew Modes, 16,631 (0x40F7) The DSP slew modes register sets the slew source for each output. The slew source can be either the DSP (digital slew) or the codec (analog slew). When these bits are set to Logic 0, the codec provides volume slew according to the ASLEW[1:0] bits in Register R34 (playback pop/click suppression register, Address 0x4028). When these bits are set to Logic 1, the slew is provided and defined by the DSP program, disabling the codec volume slew.
ADAU1761 R65: Clock Enable 0, 16,633 (0x40F9) This register disables or enables the digital clock engine for different blocks within the ADAU1761. For maximum power saving, use this register to disable blocks that are not being used. Bit 7 Reserved Bit 6 SLEWPD Bit 5 ALCPD Bit 4 DECPD Bit 3 SOUTPD Bit 2 INTPD Bit 1 SINPD Bit 0 SPPD Table 90. Clock Enable 0 Register Bits 6 Bit Name SLEWPD 5 ALCPD 4 DECPD 3 SOUTPD 2 INTPD 1 SINPD 0 SPPD Description Codec slew digital clock engine enable.
ADAU1761 Table 92. R8 and R9 Volume Settings Binary Value 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 Volume Setting (dB) −12 −11.25 −10.5 −9.75 −9 −8.25 −7.5 −6.75 −6 −5.25 −4.5 −3.75 −3 −2.25 −1.
ADAU1761 Table 94.
ADAU1761 Binary Value 01100000 01100001 01100010 01100011 01100100 01100101 01100110 01100111 01101000 01101001 01101010 01101011 01101100 01101101 01101110 01101111 01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 01111001 01111010 01111011 01111100 01111101 01111110 01111111 10000000 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 10001001 10001010 10001011 10001100 10001101 10001110 10001111 10010000 Volume Attenuation (dB) −36 −36.375 −36.75 −37.
ADAU1761 Binary Value 11000010 11000011 11000100 11000101 11000110 11000111 11001000 11001001 11001010 11001011 11001100 11001101 11001110 11001111 11010000 11010001 11010010 11010011 11010100 11010101 11010110 11010111 11011000 11011001 11011010 11011011 11011100 11011101 11011110 11011111 11100000 11100001 11100010 11100011 11100100 11100101 11100110 11100111 11101000 11101001 11101010 11101011 11101100 11101101 11101110 11101111 11110000 11110001 11110010 Volume Attenuation (dB) −72.75 −73.125 −73.
ADAU1761 Binary Value 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Volume Setting (dB) −24 −23 −22 −21 −20 −19 −18 −17 −16 −15 −14 −13 −12 −11 −10 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 Rev.
ADAU1761 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 17 16 0.30 0.23 0.18 3.65 3.50 SQ 3.35 9 8 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 1 EXPOSED PAD (BOTTOM VIEW) 0.80 MAX 0.65 TYP 12° MAX 32 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 100608-A TOP VIEW 1.00 0.85 0.
