Low Noise Stereo Codec with SigmaDSP Processing Core ADAU1781 FEATURES GENERAL DESCRIPTION 24-bit stereo audio ADC and DAC 400 mW speaker amplifier (into 8 Ω load) Programmable SigmaDSP audio processing core Wind noise detection and filtering Enhanced stereo capture (ESC) Dynamics processing Equalization and filtering Volume control and mute Sampling rates from 8 kHz to 96 kHz Stereo pseudo differential microphone input Optional stereo digital microphone input pulse-density modulation (PDM) Stereo line ou
ADAU1781 TABLE OF CONTENTS Features .............................................................................................. 1 Input Signal Path ........................................................................ 30 Applications ....................................................................................... 1 Analog-to-Digital Converters................................................... 31 General Description .........................................................................
ADAU1781 Speaker Driver Supply Trace (AVDD2) ...................................47 Audio Converter Configuration ............................................... 63 Exposed Pad PCB Design ..........................................................47 Playback Path Configuration .................................................... 68 Control Register Map .....................................................................48 Pad Configuration ................................................................
ADAU1781 SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V, digital supply = 1.5 V, unless otherwise noted; temperature = 25°C; master clock (MCLK) = 12.
ADAU1781 Parameter Left/Right Microphone PGA Gain Range Left/Right Microphone PGA Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio DIFFERENTIAL MICROPHONE INPUT TO ADC PATH Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Left/Right Microphone PGA Mute Attenuation Interchannel Gain Mismatch Off
ADAU1781 Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Beep Input Mute Attenuation Offset Error Gain Error Interchannel Gain Mismatch Beep Input PGA Gain Range Beep Playback Mixer Gain Range Power Supply Rejection Ratio MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.90 × AVDD Bias Current Source Noise in the Signal Bandwidth Test Conditions/Comments −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V; mute set by Register 0x4008, Bit 3 AVDD = 3.3 V AVDD = 3.
ADAU1781 Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Gain Error Interchannel Gain Mismatch Offset Error DAC TO SPEAKER OUTPUT PATH Differential Full-Scale Output Voltage (0 dB) Total Harmonic Distortion + Noise 4 Ω Load 8 Ω Load Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS
ADAU1781 Parameter Total Harmonic Distortion + Noise Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Differential Offset Error Mono Mixer Mute Attenuation, Beep to Mixer Path Muted REFERENCE (CM PIN) Common-Mode Reference Output Test Conditions/Comments Min 8 Ω, 1 nF load, AVDD = 1.8 V, PO = 50 mW AVDD = 3.3 V, PO = 175 mW −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.
ADAU1781 TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, PLL is active in integer mode at a 256 × fS input rate for fS = 48 kHz, analog and digital input tones are −1 dBFS with a frequency of 1 kHz. Analog input and output are simultaneously active. Pseudo differential stereo input is routed to ADCs, and DACs are routed to stereo line output with a 16 kΩ load. ADC input at −1 dBFS, DAC input at 0 dBFS. The speaker output is disabled. The serial port is configured in slave mode.
ADAU1781 Parameter DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode Factor Min Typ 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value
ADAU1781 DIGITAL TIMING SPECIFICATIONS −25°C < TA < +85°C, IOVDD = 1.62 V to 3.63 V, unless otherwise specified. Table 7. Digital Timing Parameter MASTER CLOCK tMP Duty Cycle SERIAL PORT tBIL tBIH tLIS tLIH tSIS tSIH tSODM SPI PORT fCCLK,R fCCLK,R fCCLK,W fCCLK,W tCCPL tCCPH tCLS tCLH tCLPH tCDS tCDH tCOD I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tSCR tSCF tSDR tSDF tBFT DIGITAL MICROPHONE tDCF tDCR tDDV tDDH tMIN 50 30 Limit tMAX Unit Description 90.
ADAU1781 Digital Timing Diagrams tLIH tBIH BCLK tBIL tLIS LRCLK tSIS DAC_SDATA LEFT-JUSTIFIED MODE MSB MSB – 1 tSIH tSIS DAC_SDATA I2S MODE MSB tSIH tSIS tSIS DAC_SDATA RIGHT-JUSTIFIED MODE LSB MSB tSIH tSIH 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 08314-002 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 2.
ADAU1781 tCLS tCLH tCLPH tCCPL tCCPH CLATCH CCLK CDATA tCDH tCDS COUT 08314-004 tCOD Figure 4. SPI Port Timing tSDR tSCH tDS tSCH SDA tSDF tSCR 08314-005 tSCLH SCL tSCLL tSCS tSCF tBFT 2 Figure 5. I C Port Timing tDCF tDCR CLK tDDH DATA2 tDDV tDDV DATA1 DATA2 08314-106 DATA1/ DATA2 DATA1 tDDH Figure 6. Digital Microphone Timing Rev.
ADAU1781 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Power Supply (AVDD1 = AVDD2) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.9 V ±20 mA –0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −25°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
ADAU1781 32 31 30 29 28 27 26 25 MICBIAS BEEP LMIC/LMICN/MICD1 LMICP RMICP RMIC/RMICN/MICD2 AOUTL AOUTR PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADAU1781 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 NC AGND2 SPP NC SPN AVDD2 MCKO MCKI NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1781 GROUNDS.
ADAU1781 Type1 D_OUT PWR A_OUT Pin No. 18 19 20 21 22 23 24 25 26 27 Mnemonic MCKO AVDD2 SPN NC SPP AGND2 NC AOUTR AOUTL RMIC/RMICN/MICD2 A_OUT A_OUT A_IN 28 29 30 RMICP LMICP LMIC/LMICN/MICD1 A_IN A_IN A_IN 31 32 BEEP MICBIAS THERM_PAD (Exposed Pad) A_IN PWR 1 A_OUT PWR Description Master Clock Output. Analog Power Supply. Should be equivalent to AVDD1. Speaker Amplifier Negative Signal Output. No Connect. Speaker Amplifier Positive Signal Output. Speaker Amplifier Ground. No Connect.
ADAU1781 0 0.10 –10 0.08 –20 0.06 –30 0.04 MAGNITUDE (dBFS) –40 –50 –60 –70 0.02 0 –0.02 –0.04 –80 –0.06 –90 –0.08 –100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (NORMALIZED TO fS) 08314-009 –0.10 0 Figure 8. ADC Decimation Filter, 64× Oversampling, Normalized to fS 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 08314-012 MAGNITUDE (dBFS) TYPICAL PERFORMANCE CHARACTERISTICS 0.50 FREQUENCY (NORMALIZED TO fS) Figure 11.
0 0.05 –10 0.04 –20 0.03 –30 0.02 MAGNITUDE (dBFS) –40 –50 –60 –70 0.01 0 –0.01 –0.02 –80 –0.03 –90 –0.04 –0.05 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (NORMALIZED TO fS) 08314-015 –100 Figure 14. DAC Interpolation Filter, 64× Oversampling, Normalized to fS 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY (NORMALIZED TO fS) 08314-018 MAGNITUDE (dBFS) ADAU1781 Figure 17.
ADAU1781 0 0 –10 –20 –20 –40 THD + N (dB) THD + N (dB) –30 –50 –60 –40 –60 –70 –80 –80 –90 1 10 100 SPEAKER OUTPUT POWER (mW) 600 Figure 20. THD + N vs. Speaker Output Power, 8 Ω Load, 3.3 V Supply 1 10 SPEAKER OUTPUT POWER (mW) 100 08314-122 –100 08314-121 –100 Figure 21. THD + N vs. Speaker Output Power, 8 Ω Load, 1.8 V Supply Rev.
ADAU1781 SYSTEM BLOCK DIAGRAMS IOVDD 10µF AVDD1 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.1µF 49.9kΩ AVDD2 AVDD1 DVDDOUT 10µF IOVDD DIFFERENTIAL INPUT (LEFT) MICBIAS + 100pF LMIC/LMICN/MICD1 SPN LMICP SPP 10kΩ 10kΩ 10Ω 220µF AOUTL 10µF STEREO SINGLE-ENDED HEADPHONE OUTPUT + AOUTR 49.9kΩ 10kΩ ADAU1781 100pF DIFFERENTIAL INPUT (RIGHT) 10µF 10kΩ RMIC/RMICN/MICD2 49.
ADAU1781 AVDD1 IOVDD 10µF 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.1µF 2kΩ AVDD2 AVDD1 DVDDOUT MICBIAS IOVDD MICBIAS + 100pF SPN 0.1µF 10kΩ SPP ANALOG MIC 1 LMIC/LMICN/MICD1 10µF 10kΩ LMICP AOUTR 100pF MICBIAS ANALOG MIC 2 10kΩ 0.1µF 10kΩ 10kΩ 10Ω 220µF 10µF + RMIC/RMICN/MICD2 49.9kΩ LEFT_OUT 10kΩ CM ADAU1781 2kΩ 10Ω 220µF AOUTL CM + 49.
ADAU1781 IOVDD 10µF AVDD1 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.1µF AVDD2 AVDD1 DVDDOUT IOVDD MICBIAS + 100pF SPN SINGLE-ENDED STEREO INPUT 10kΩ SPP 10kΩ 10µF 49.9kΩ 10Ω 220µF AOUTL LMIC/LMICN/MICD1 CM AOUTR LEFT_OUT + 1kΩ STEREO SINGLE-ENDED HEADPHONE OUTPUT LMICP CM ADAU1781 10kΩ 100pF 10µF 1kΩ RMIC/RMICN/MICD2 49.
ADAU1781 AVDD1 IOVDD 10µF 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.
ADAU1781 THEORY OF OPERATION The ADAU1781 is a low power audio codec with an integrated, programmable SigmaDSP audio processing core. It is an all-in-one package that offers high quality audio, low power, small size, and many advanced features. The stereo ADC and stereo DAC each have a dynamic range (DNR) performance of at least 96.5 dB and a total harmonic distortion plus noise (THD + N) performance of at least −90 dB.
ADAU1781 STARTUP, INITIALIZATION, AND POWER POWER-UP SEQUENCE This section details the procedure for setting up the ADAU1781 properly. Figure 26 provides an overview of how to initialize the IC. If AVDD1 and AVDD2 are from the same supply, they can power up simultaneously. If AVDD1 and AVDD2 are from separate supplies, then AVDD1 should be powered up first. IOVDD should be applied simultaneously with AVDD1, if possible.
ADAU1781 CLOCK GENERATION AND MANAGEMENT The ADAU1781 uses a flexible clocking scheme that enables the use of many different input clock rates. The PLL can be bypassed or used, resulting in two different approaches to clock management. For more information about clocking schemes, PLL configuration, and sampling rates, see the Clocking and Sampling Rates section. Case 1: PLL Is Bypassed If the PLL is bypassed, the core clock is derived directly from the master clock (MCLK) input.
ADAU1781 CLOCKING AND SAMPLING RATES SOUND ENGINE FRAME RATE fS/ 0.5, 1, 1.5, 2, 3, 4, 6 AUTOMATICALLY SET TO 1024 × fS WHEN PLL CLOCK SOURCE SELECTED CONVERTER SAMPLING RATE ADCs DACs fS/ 0.5, 1, 1.5, 2, 3, 4, 6 SERIAL PORT SAMPLING RATE SERIAL DATA INPUT/OUTPUT PORTS ADC_SDATA/GPIO1 fS/ 0.5, 1, 1.
ADAU1781 Table 14 and Table 15 list the sampling rate divisions for common base sampling rates. Fractional Mode Fractional mode is used when the MCLK is a fractional (R + (N/M)) multiple of the PLL output. Table 14. Base Sampling Rate Divisions for fS = 48 kHz Base Sampling Frequency fS = 48 kHz Sampling Rate Scaling fS/1 fS/6 fS/4 fS/3 fS/2 fS/1.5 fS/0.5 Sampling Rate 48 kHz 8 kHz 12 kHz 16 kHz 24 kHz 32 kHz 96 kHz Table 15. Base Sampling Rate Divisions for fS = 44.
ADAU1781 The ADC and DAC sampling rate can be set in Register 16407 (0x4017), Converter Control 0, Bits[2:0], converter sampling rate. The SigmaDSP core sampling rate and serial port sampling rate are similarly set in Register 16619 (0x40EB), SigmaDSP core frame rate, Bits[3:0], SigmaDSP core frame rate, and Register 16632 (0x40F8), serial port sampling rate, Bits[2:0], serial port control sampling rate, respectively. Table 18. Sampling Rates for 256 × 48 kHz Core Clock Core Clock 12.
ADAU1781 RECORD SIGNAL PATH A BEEP pin input can also be amplified or muted by a PGA, up to 32 dB in Register 16392 (0x4008), digital microphone and analog beep control. The beep input must be enabled in Register 16400 (0x4010), microphone bias control and beep enable. BEEP PGA LMIC/LMICN/ MICD1 Microphone Bias PGA LMICP LEFT ADC The MICBIAS pin provides a voltage reference for electret microphones. Register 16400 (0x4010), microphone bias control and beep enable, sets the operation mode of this pin.
ADAU1781 ANALOG-TO-DIGITAL CONVERTERS The ADAU1781 uses two 24-bit Σ-Δ analog-to-digital converters (ADCs) with selectable oversampling rates of either 64× or 128×. The full-scale input to the ADCs depends on AVDD1. At 3.3 V, the full-scale input level is 1.0 V rms. Inputs greater than the full-scale value result in clipping and distortion.
ADAU1781 PLAYBACK SIGNAL PATH LINE OUT AMPLIFIER The speaker outputs are derived from the mono playback mixer, which sums the right and left DAC outputs and mixes with the beep signal. The mixer can be controlled in Register 16415 (0x401F), playback mono mixer control.
ADAU1781 CONTROL PORTS The ADAU1781 can operate in one of two control modes: I2C control or SPI control. The ADAU1781 has both a 4-wire SPI control port and a 2-wire I2C bus control port. Each can be used to set the registers. The part defaults to I2C mode but can be put into SPI control mode by pulling the CLATCH pin low three times. The control port is capable of full read/write operation for all addressable registers.
ADAU1781 Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, the ADAU1781 immediately jumps to the idle condition. During a given SCL high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition.
ADAU1781 I2C Read and Write Operations of the subaddress, the master must issue a repeated start command followed by the chip address byte with the R/W bit set to 1 (read). This causes the ADAU1781 SDA to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU1781. Figure 39 shows the timing of a single-word write operation. Every ninth clock pulse, the ADAU1781 issues an acknowledge by pulling SDA low.
ADAU1781 Data Bytes SPI PORT By default, the ADAU1781 is in I2C mode, but can be put into SPI control mode by pulling CLATCH low three times. The SPI port uses a 4-wire interface, consisting of CLATCH, CCLK, CDATA, and COUT signals, and is always a slave port. The CLATCH signal goes low at the beginning of a transaction and high at the end of a transaction. The CCLK signal latches CDATA on a low-to-high transition.
ADAU1781 CLATCH CDATA BYTE 0 BYTE 1 BYTE 2 08314-042 CCLK BYTE 3 Figure 43. SPI Write to ADAU1781 Clocking (Single-Write Mode) CLATCH CCLK COUT BYTE 1 BYTE 0 BYTE 3 HIGH-Z DATA Figure 44. SPI Read from ADAU1781 Clocking (Single-Read Mode) Rev.
ADAU1781 SERIAL DATA INPUT/OUTPUT PORTS The serial data clocks must be synchronous with the ADAU1781 master clock input. The LRCLK and BCLK pins are used to clock both the serial input and output ports. The ADAU1781 can be set as the master or the slave in a system. Because there is only one set of serial data clocks, the input and output ports must always be both master or both slave.
ADAU1781 LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK LSB MSB LSB MSB 08314-045 SDATA 1/fS 2 Figure 46. I S Mode—16 Bits to 24 Bits per Channel MSB LSB MSB LSB 08314-046 SDATA RIGHT CHANNEL LEFT CHANNEL LRCLK BCLK 1/fS Figure 47. Left-Justified Mode—16 Bits to 24 Bits per Channel RIGHT CHANNEL SDATA MSB LSB MSB LSB 08314-047 LEFT CHANNEL LRCLK BCLK 1/fS Figure 48.
ADAU1781 GENERAL-PURPOSE INPUT/OUTPUTS The serial data input/output pins are shared with the generalpurpose input/output function. Each of these four pins can be set to only one function. The function of these pins is set in Register 16628 (0x40F4), serial data/GPIO pin configuration. The GPIO pins can be used as either inputs or outputs. These pins are readable and can be set either through the control interface or directly by the SigmaDSP core.
ADAU1781 DSP CORE SIGNAL PROCESSING The ADAU1781 is designed to provide all audio signal processing functions commonly used in stereo or mono low power record and playback systems. The signal processing flow is designed using the SigmaStudio™ software, which allows graphical entry and real-time control of all signal processing functions. Many of the signal processing functions are coded using full, 56-bit, double-precision arithmetic data. The input and output word lengths of the DSP core are 24 bits.
ADAU1781 NUMERIC FORMATS DSP systems commonly use a standard numeric format. Fractional number systems are specified by an A.B format, where A is the number of bits to the left of the decimal point and B is the number of bits to the right of the decimal point. A digital clipper circuit is used between the output of the DSP core and the DACs or serial port outputs (see Figure 52). This circuit clips the top four bits of the signal to produce a 24-bit output with a range of 1.0 (minus 1 LSB) to −1.0.
08314-202 ADAU1781 Figure 53. SigmaStudio Screen Shot Rev.
ADAU1781 PROGRAM RAM, PARAMETER RAM, AND DATA RAM Table 27. RAM Map and Read/Write Modes Memory Parameter RAM Program RAM Size 512 × 32 512 × 40 Address Range 0 to 511 (0x0000 to 0x01FF) 1024 to 1535 (0x0400 to 0x05FF) Table 27 shows the RAM map (the ADAU1781 register map is provided in the Control Register Map section). The address space encompasses a set of registers and three RAMs: program, parameter, and data.
ADAU1781 Table 28. Parameter RAM Read/Write Format (Single Address) Byte 0 CHIP_ADR[6:0], R/W Byte 1 PARAM_ADR[15:8] Byte 2 PARAM_ADR[7:0] Byte 3 0000, PARAM[27:24] Bytes[4:6] PARAM[23:0] Table 29. Parameter RAM Block Read/Write Format (Burst Mode) Byte 0 CHIP_ADR[6:0], R/W Byte 1 PARAM_ADR[15:8] Byte 2 PARAM_ADR[7:0] Byte 3 0000, PARAM[27:24] Bytes[4:6] PARAM[23:0] <—PARAM_ADR—> Bytes[7:10] Bytes[11:14] PARAM_ADR + 1 PARAM_ADR + 2 Table 30.
ADAU1781 When the values of signal processing parameters are changed abruptly in real time, they sometimes cause pop and click sounds to appear on the audio outputs. To avoid pops and clicks, some algorithms in SigmaStudio implement a software slew functionality. Algorithms using software slew set a target value for a parameter and continuously update the value of that parameter until it reaches the target.
ADAU1781 APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS GROUNDING Each analog and digital power supply pin should be bypassed to its nearest appropriate ground pin with a single 100 nF capacitor. The connections to each side of the capacitor should be as short as possible, and the trace should stay on a single layer with no vias.
ADAU1781 CONTROL REGISTER MAP All registers except the PLL control register are 1-byte write and read registers. Table 33.
ADAU1781 CLOCK MANAGEMENT, INTERNAL REGULATOR, AND PLL CONTROL Register 16384 (0x4000), Clock Control The clock control register sets the clocking scheme for the ADAU1781. The system clock can be generated from either the PLL or directly from the MCKI (master clock input) pin. Additionally, the MCKO (master clock output) pin can be configured. Bits[6:5], MCKO Frequency These bits set the frequency to be output on MCKO as a multiple of the base sampling frequency (32×, 64×, 128×, or 256×).
ADAU1781 Register 16385 (0x4001), Regulator Control Bits[2:1], Regulator Output Level Bits[10:9], Input Divider These bits set the regulated voltage output for the digital core, DVDDOUT. After the initialization sequence has completed, the regulator output is set to 1.4 V. The recommended regulator output level when the device begins to process audio is 1.5 V. Therefore, this register should be set to 1.5 V when the SigmaDSP core is being configured.
ADAU1781 Table 38.
ADAU1781 Table 39. Fractional PLL Parameter Settings for fS = 44.1 kHz (fS = 44.1 kHz, Core Clock = 256 × 44.1 kHz, PLL Clock = 45.1584 MHz) MCLK Input (MHz) 12 13 14.4 19.2 19.68 19.8 Input Divider (X) 1 1 1 1 1 1 Integer (R) 3 3 3 2 2 2 Denominator (M) 625 8125 125 125 2035 1375 Numerator (N) 477 3849 17 44 302 386 Table 40. Fractional PLL Parameter Settings for fS = 48 kHz (fS = 48 kHz, Core Clock = 256 × 48 kHz, PLL Clock = 49.152 MHz) MCLK Input (MHz) 12 13 14.4 19.2 19.68 19.
ADAU1781 RECORD PATH CONFIGURATION Bit 3, Beep Input Mute Register 16392 (0x4008), Digital Microphone and Analog Beep Control This bit mutes the beep input. This register controls the digital microphone settings and the analog beep input gain. Bits[5:4], Digital Microphone Enable These bits control the enable function for the stereo digital microphones. The analog front end is powered down when using a digital microphone.
ADAU1781 Register 16393 (0x4009), Record Power Management Bits[6:5], Mixer Amplifier Boost This register manages the power consumption for the record path. In particular, the current distribution for the mixer boosts, ADC, front-end mixer, and PGAs can be set in one of four modes. The four modes of operation available that affect the performance of the device are normal operation, power saving, enhanced performance, and extreme power saving. Normal operation has a base current of 2.
ADAU1781 Register 16398 (0x400E), Record Gain Left PGA The record gain left PGA control register controls the left channel input PGA. This register configures the input for either differential or single-ended signals and sets the left channel input recording volume. input pin (LMICP) is disabled, and the complementary input of the PGA is switched to common mode. Bit 1, Record Path Left Mute This bit mutes the left channel input PGA.
ADAU1781 Register 16399 (0x400F), Record Gain Right PGA The record gain right PGA control register controls the right channel input PGA. This register configures the input for either differential or single-ended signals and sets the right channel input recording volume. input pin (RMICP) is disabled, and the complementary input of the PGA is switched to common mode. Bit 1, Record Path Right Mute This bit mutes the entire right channel input PGA.
ADAU1781 Register 16400 (0x4010), Microphone Bias Control and Beep Enable Bit 4, Beep Input Enable This bit enables the beep signal, which is input to the BEEP pin. Setting this bit to 0 mutes the beep signal for all output paths. Bit 3, Microphone High Performance Bit 2, Microphone Gain Provides two voltage bias options, 0.65 × AVDD1 and 0.90 × AVDD1. A higher bias contributes to a higher microphone gain. The maximum current that can be drawn from MICBIAS is 5 mA.
ADAU1781 SERIAL PORT CONFIGURATION Bits[2:1], Channels per Frame Register 16405 (0x4015), Serial Port Control 0 Bit 5, LRCLK Mode These bits set the number of channels contained in the data stream (see Figure 61). The possible choices are stereo (used in standard I2S signals), TDM 4 (a 4-channel time division multiplexed stream), or TDM 8 (an 8-channel time division multiplexed stream).
ADAU1781 BCLK POLARITY LRCLK BCLK SDATA LRCLK 08314-055 BCLK SDATA Figure 59. Serial Port BCLK Polarity LRCLK POLARITY LRCLK R L R L R 08314-056 L LRCLK Figure 60. Serial Port LRCLK Polarity 1/fLRCLK LRCLK 2 1 1 TDM 4 CHANNELS TDM 8 CHANNELS 2 2 1 3 3 4 4 5 6 7 8 08314-057 STEREO CHANNELS Figure 61. Channels per Frame 1/fLRCLK LRCLK FIRST PAIR 2 FIRST PAIR 1 3 SECOND PAIR 2 3 4 THIRD PAIR 5 Figure 62. TDM Channel Pairs Rev.
ADAU1781 Register 16406 (0x4016), Serial Port Control 1 Bits[7:5], Number of Bit Clock Cycles per Frame Bit 2, MSB Position These bits set the number of BCLK cycles contained in one LRCLK period. The frequency of BCLK is calculated as the number of bit clock cycles per frame times the sample rate of the serial port in hertz. Figure 63 and Figure 64 show examples of different settings for these bits.
ADAU1781 1/fLRCLK BCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 08314-059 LRCLK Figure 63. Example: 32 BCLK Cycles per Frame 1/fLRCLK 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Figure 64.
ADAU1781 1/fLRCLK LRCLK SERIAL DATA (DELAY BY 1) SERIAL DATA (DELAY BY 8) 1 2 3 4 9 11 14 16 17 M 19 21 24 26 27 31 33 34 35 L M 39 42 44 45 47 49 M L M 37 51 54 56 57 59 61 63 L M L L M L 08314-064 BCLK SERIAL DATA (DELAY BY 0) Figure 68.
ADAU1781 AUDIO CONVERTER CONFIGURATION Bit 4, DAC Oversampling Ratio Register 16407 (0x4017), Converter Control 0 Bits[6:5], On-Chip DAC Data Selection in TDM Mode This bit sets the oversampling ratio of the DAC relative to the audio sample rate. The higher rate yields slightly better audio quality but increases power consumption. These bits set the position of the DAC input channels on a TDM stream. In TDM 4 mode, valid settings are first pair or second pair.
ADAU1781 1/fLRCLK LRCLK FIRST PAIR RIGHT FIRST PAIR SECOND PAIR LEFT FOURTH PAIR THIRD PAIR RIGHT 08314-066 TDM 8 CHANNELS SECOND PAIR LEFT TDM 4 CHANNELS Figure 70. Example of Left Channel First, First Pair TDM Setting 1/fLRCLK LRCLK FIRST PAIR TDM 4 CHANNELS FIRST PAIR SECOND PAIR RIGHT TDM 8 CHANNELS RIGHT LEFT THIRD PAIR FOURTH PAIR LEFT 08314-067 SECOND PAIR Figure 71.
ADAU1781 Register 16408 (0x4018), Converter Control 1 Bits[1:0], On-Chip ADC Data Selection in TDM Mode These bits set the position of the ADC output channels on a TDM stream. In TDM 4 mode, valid settings are first pair or second pair. In TDM 8 mode, valid settings are first pair, second pair, third pair, or fourth pair. These bits should be set in conjunction with Register 16406 (0x4016), Serial Port Control 1, Bit 4, ADC channel position in TDM, to select where the data should appear in the TDM stream.
ADAU1781 Bit 3, Digital Microphone Channel Swap Register 16409 (0x4019), ADC Control Bit 6, Invert Input Polarity This bit enables an optional polarity inverter in the ADC path, which is an amplifier with a gain of −1, representing a 180° phase shift. Bit 5, High-Pass Filter Select This bit enables an optional high-pass filter in the ADC path, with a cutoff frequency of 2 Hz when fS = 48 kHz. The cutoff frequency scales linearly with fS.
ADAU1781 Register 16410 (0x401A), Left ADC Attenuator Bits[7:0], Left ADC Digital Attenuator Register 16411 (0x401B), Right ADC Attenuator Bits[7:0], Right ADC Digital Attenuator These bits control a 256-step, logarithmically spaced volume control from 0 dB to −95.625 dB, in increments of 0.375 dB. When a new value is entered into this register, the volume control slews gradually to the new value, avoiding pops and clicks in the process. The slew ramp is logarithmic, incrementing 0.375 dB per audio frame.
ADAU1781 Register 16414 (0x401E), Playback Mixer Right Control Bit 6, Right DAC Mute PLAYBACK PATH CONFIGURATION Register 16412 (0x401C), Playback Mixer Left Control Bit 5, Left DAC Mute This bit mutes the left DAC output. It does not have any slew and is updated immediately when the register write has been completed. This results in an abrupt cutoff of the audio output and should therefore be preceded by a soft mute in the SigmaDSP core or a slew mute using the DAC attenuator.
ADAU1781 Register 16415 (0x401F), Playback Mono Mixer Control Bit 7, Left DAC Mute This bit mutes the left DAC output, but does not power down the DAC. Use of this bit does not result in power savings. Bit 6, Right DAC Mute This bit mutes the right DAC output, but does not power down the DAC. Use of this bit does not result in power savings. Bits[5:2], Mono Playback Beep Gain These bits set the gain of the beep output signal in mono mode.
ADAU1781 Register 16421 (0x4025), Left Line Output Mute Bit 1, Left Line Output Mute Register 16422 (0x4026), Right Line Output Mute Bit 1, Right Line Output Mute This bit mutes the left line output. It does not have any effect on the speaker outputs. This bit mutes the right line output. It does not have any effect on the speaker outputs. Table 57. Left Line Output Mute Register Bits [7:2] 1 0 Description Reserved Left line output mute (active low) 0: muted 1: unmuted Reserved Default 0 Table 58.
ADAU1781 Register 16423 (0x4027), Playback Speaker Output Control Bits[7:6], Speaker Output Gain Control Register 16424 (0x4028), Beep Zero-Crossing Detector Control Bits[4:3], Detector Timeout These bits control the gain of the speaker output. In general, this parameter should be tuned at a system level, set once during system initialization and not altered during operation of the system.
ADAU1781 Register 16425 (0x4029), Playback Power Management Bits[5:4], DAC Bias Control This register controls the unity current supplied to each functional block described. Within the functional blocks, the current can be multiplied. Normal operation has a base current of 2.5 μA, enhanced performance has a base current of 3 μA, power saving has a base current of 2 μA, and extreme power saving has a base current of 1.5 μA.
ADAU1781 Bit 5, Invert Input Polarity Register 16426 (0x402A), DAC Control Bits[7:6], Mono Mode These bits control the output mode of the DAC. Setting these bits to 00 outputs two distinct channels, left and right. Setting these bits to 01 outputs the left input channel on both the left and right outputs, and the right input channel is lost. Setting these bits to 10 outputs the right input channel on both the left and right outputs, and the left input channel is lost.
ADAU1781 Register 16427 (0x402B), Left DAC Attenuator Bits[7:0], Left DAC Digital Attenuator Register 16428 (0x402C), Right DAC Attenuator Bits[7:0], Right DAC Digital Attenuator These bits control a 256-step, logarithmically spaced volume control from 0 dB to −95.625 dB, in increments of 0.375 dB. When a new value is entered into this register, the volume control slews gradually to the new value, avoiding pops and clicks in the process. The slew ramp is logarithmic, incrementing 0.375 dB per audio frame.
ADAU1781 PAD CONFIGURATION Figure 73 shows a block diagram of the pad design for the GPIO/serial port and communications port pins.
ADAU1781 Bits[3:2], LRCLK Pad Pull-Up/Pull-Down Register 16429 (0x402D), Serial Port Pad Control 0 Bits[7:6], ADC_SDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[5:4], DAC_SDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ.
ADAU1781 Bit 1, LRCLK Pin Drive Strength Register 16430 (0x402E), Serial Port Pad Control 1 Bit 3, ADC_SDATA Pin Drive Strength This bit sets the drive strength of the ADC_SDATA pin. Low mode yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when IOVDD = 1.8 V. Bit 2, DAC_SDATA Pin Drive Strength This bit sets the drive strength of the DAC_SDATA pin. Low mode yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.
ADAU1781 Bits[3:2], SCL/CCLK Pad Pull-Up/Pull-Down Register 16431 (0x402F), Communication Port Pad Control 0 Bits[7:6], CDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[5:4], CLATCH Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ.
ADAU1781 Bit 1, SCL/CCLK Pin Drive Strength Register 16432 (0x4030), Communication Port Pad Control 1 Bit 3, CDATA Pin Drive Strength This bit sets the drive strength of the CDATA pin. Low mode yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when IOVDD = 1.8 V. Bit 2, CLATCH Pin Drive Strength This bit sets the drive strength of the CLATCH pin. Low mode yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.
ADAU1781 Bit 1, MCKO Pull-Up Enable Register 16433 (0x4031), MCKO Control Bit 2, MCKO Pin Drive Strength This bit sets the drive strength of the MCKO pin. Low mode yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when IOVDD = 1.8 V. This bit enables or disables a weak pull-up device on the pad. The effective resistance of the pull-up is nominally 240 kΩ.
ADAU1781 Register 16434 (0x4032), Dejitter Control Bits[7:0], Dejitter Window Size The dejitter control register not only allows the size of the dejitter window to be set, but also allows all dejitter circuits in the device to be activated or bypassed. Dejitter circuits protect against duplicate samples or skipped samples due to jitter from the serial ports in slave mode.
ADAU1781 DIGITAL SUBSYSTEM CONFIGURATION Bit 3, Serial Output Routing Register 16512 (0x4080), Digital Power-Down 0 Bit 7, ADC Engine Setting this bit to 0 disables the routing paths for the record signal path, which goes from the SigmaDSP core to the serial port output. Setting this bit to 0 disables the ADCs and the digital microphone inputs.
ADAU1781 Register 16513 (0x4081), Digital Power-Down 1 Bit 3, Output Precharge Bit 1, Digital Microphone The output precharge system allows the outputs to be biased before they are enabled and prevents pops or clicks from appearing on the output. This bit should be set to 1 at all times. Bit 0, DAC Engine Setting this bit to 0 disables the digital microphone input. Setting this bit to 0 disables the DACs.
ADAU1781 Register 16582 to Register 16586 (0x40C6 to 0x40CA), GPIO Pin Control Bits[3:0], GPIO Pin Function SigmaDSP core). In order for GPIO0 through GPIO3 to be used, they should be configured as 1001 or 1010 (outputs set by the I2C/SPI port). The GPIO pin control register sets the functionality of each GPIO pin as depicted in Table 74. GPIO0 to GPIO3 use the same pins as the serial port and must be enabled in Register 16628 (0x40F4), serial data/GPIO pin configuration. Pin 7 is a dedicated GPIO.
ADAU1781 Register 16617 and Register 16618 (0x40E9 and 0x40EA), Nonmodulo These registers set the boundary for the nonmodulo RAM space used by the SigmaDSP core. An appropriate value is automatically loaded to this register during initialization. It should not be modified for any reason. Register 16619 (0x40EB), SigmaDSP Core Frame Rate Bits[3:0], SigmaDSP Core Frame Rate These bits set the frequency of the frame start pulse, which is delivered to the SigmaDSP core to begin processing on each audio frame.
ADAU1781 Register 16626 (0x40F2), Serial Input Route Control Bits[3:0], Input Routing These bits select which serial data input channels are routed to the DACs (see Figure 74). Table 78.
ADAU1781 Register 16627 (0x40F3), Serial Output Route Control Bits[3:0], Output Routing These bits select where the ADC outputs are routed in the serial data stream (see Figure 74). Table 79. Serial Output Route Control Register Bits [7:4] [3:0] Default 0000 Lx = left side of Channel x; Rx = right side of Channel x. 1/fLRCLK LRCLK L0 STEREO CHANNELS L0 TDM 4 CHANNELS TDM 8 CHANNELS R0 L0 R0 R0 L1 L1 R1 L2 Figure 74. Serial Port Routing Control Rev.
ADAU1781 Register 16628 (0x40F4), Serial Data/GPIO Pin Configuration Bits[3:0], GPIO[0:3] Before going into standby mode, the following sequence must be performed: The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1, then the GPIO[0:3] pins become GPIO interfaces to the SigmaDSP core. If these bits are set to 0, they remain LRCLK, BCLK, or serial port data pins, respectively.
ADAU1781 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 12° MAX EXPOSED PAD (BOTTOM VIEW) 17 16 0.80 MAX 0.65 TYP 0.30 0.23 0.18 3.65 3.50 SQ 3.35 9 8 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 1 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 100608-A TOP VIEW 1.00 0.85 0.
ADAU1781 NOTES Rev.
ADAU1781 NOTES Rev.
ADAU1781 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08314-0-1/11(B) Rev.