Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) LQFP 80

16-Channel High Performance

Differential Output, 192 kHz, 24-Bit DAC

Data Sheet

ADAU1966

Rev. D

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FEATURES

118 dB DAC dynamic range and SNR

−98 dB THD + N

Differential voltage DAC output

2.5 V digital, 5 V analog and 3.3 V or 5 V I/O supplies

521 mW total (32.6 mW/channel) quiescent power

PLL generated or direct MCLK master clock

Low EMI design

Linear regulator driver to generate digital supply

Supports 24-bit and 32 kHz to 192 kHz sample rates

Low propagation 192 kHz sample rate mode

Log volume control with autoramp function

Temperature sensor with digital readout ±3°C accuracy

SPI and I

C controllable for flexibility

Software-controllable clickless mute

Software power-down

Right-justified, left-justified, I

S, and TDM modes

Master and slave modes with up to 16-channel input/output

80-lead LQFP package

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Home theater systems

Digital audio effects processors

GENERAL DESCRIPTION

The ADAU1966 is a high performance, single-chip DAC that

provides 16 digital-to-analog converters (DACs) with differen-

tial output using the Analog Devices, Inc., patented multibit

sigma-delta (Σ-Δ) architecture. An SPI/I

C port is included,

allowing a microcontroller to adjust volume and many other

parameters. The ADAU1966 operates from 2.5 V digital, 5 V

analog and 3.3 V or 5 V input/output supplies. A linear regulator

is included to generate the digital supply voltage from the analog

supply voltage. The ADAU1966 is available in an 80-lead LQFP

package.

The ADAU1966 is designed for low EMI. This consideration is

apparent in both the system and circuit design architectures.

By using the on-board PLL to derive the internal master clock

from an external LRCLK, the ADAU1966 can eliminate the

need for a separate high frequency master clock and can be

used with or without a bit clock. The DACs are designed using

the latest Analog Devices continuous time architectures to

further minimize EMI. By using 2.5 V digital supplies, power

consumption is minimized, and the digital waveforms are a

smaller amplitude, further reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

SERIAL DATA PORT

DIGITAL AUDIO

INPUT

PRECISION

VOLTAGE

REFERENCE

INTERNAL

TEMP

SENSOR

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL)

SPI/I

CONTROL PORT

CONTROL DATA

INPUT/OUTPUT

ADAU1966

DIFFERENTIAL

ANALOG

AUDIO

OUTPUTS

DIFFERENTIAL

ANALOG

AUDIO

OUTPUTS

DAC

DIGITAL

FILTER

AND

VOLUME

CONTROL

DIGITAL

FILTER

AND

VOLUME

CONTROL

SDATA

CLOCKS

09434-001

Figure 1.

Summary of content (52 pages)

PAGE 1
6-Channel High Performance Differential Output, 192 kHz, 24-Bit DAC ADAU1966 Data Sheet GENERAL DESCRIPTION FEATURES The ADAU1966 is a high performance, single-chip DAC that provides 16 digital-to-analog converters (DACs) with differential output using the Analog Devices, Inc., patented multibit sigma-delta (Σ-Δ) architecture. An SPI/I2C port is included, allowing a microcontroller to adjust volume and many other parameters. The ADAU1966 operates from 2.5 V digital, 5 V analog and 3.
PAGE 2
ADAU1966 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Block Power-Down and Thermal Sensor Control 1 Register27 Applications ....................................................................................... 1 Power-Down Control 2 Register .............................................. 28 General Description .........................................................................
PAGE 3
Data Sheet ADAU1966 REVISION HISTORY 12/13—Rev. C to Rev. D Changes to Features Section ............................................................ 1 Changes to General Description ..................................................... 1 Changes to Specifications Section................................................... 4 Deleted Table 3 and Table 4; Renumbered Sequentially .............. 5 Changes to Table 5 ............................................................................
PAGE 4
ADAU1966 Data Sheet SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, load capacitance (digital output) = 20 pF, load current (digital output) = ±1 mA or 1.5 kΩ to ½ DVDD supply, input voltage high = 2.0 V, input voltage low = 0.
PAGE 5
Data Sheet ADAU1966 Specifications guaranteed at AVDDx = 5 V and an ambient temperature of 105°C. Supply voltages = AVDDx = 5 V, DVDD = 2.5 V, ambient temperature 1 (TA) = 105°C, unless otherwise noted. Table 2.
PAGE 6
ADAU1966 Data Sheet POWER SUPPLY SPECIFICATIONS Table 5. Parameter SUPPLIES Voltage Analog Current—AVDD = 5.0 V Normal Operation Power-Down Digital Current—DVDD = 2.5 V Normal Operation Power-Down PLL Current—PLLVDD = 2.5 V Normal Operation Power-Down IO Current—IOVDD = 3.
PAGE 7
Data Sheet Parameter Propagation Delay ADAU1966 Mode 48 kHz mode, typical at 48 kHz 96 kHz mode, typical at 96 kHz 192 kHz mode, typical at 192 kHz 192 kHz low delay mode, typical at 192 kHz Factor 25/fS 11/fS 8/fS 2/fS Min Typ 521 115 42 10 Max Unit µs µs µs µs TIMING SPECIFICATIONS −40°C < TA < +105°C, DVDD = 2.5 V ± 10%. Table 7.
PAGE 8
ADAU1966 Data Sheet Parameter DAC SERIAL PORT tDBH tDBL tDLS tDLH tDLS tDDS tDDH Description See Figure 19 DBCLK high, slave mode DBCLK low, slave mode DLRCLK setup, time to DBCLK rising, slave mode DLRCLK hold from DBCLK rising, slave mode DLRCLK skew from DBCLK falling, master mode DSDATAx setup to DBCLK rising DSDATAx hold from DBCLK rising tDS tSCH Min 10 10 10 5 −8 10 5 tSCH SDA SCL tBFT tSCLL tSF tSCS Figure 2. I2C Timing Diagram Rev.
PAGE 9
Data Sheet ADAU1966 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Analog (AVDD) Input/Output (IOVDD) Digital (DVDD) PLL (PLLVDD) VSUPPLY Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +5.5 V −0.3 V to +5.5 V −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +6.0 V ±20 mA –0.3 V to AVDD + 0.3 V −0.3 V to IOVDD + 0.
PAGE 10
ADAU1966 Data Sheet DAC12N DAC12P DAC11N DAC11P DAC10N DAC10P DAC9N DAC9P DAC8N DAC8P DAC7N DAC7P DAC6N DAC6P DAC5N DAC5P TS_REF CM AGND2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 DAC_BIAS3 1 60 DAC_BIAS2 59 DAC_BIAS1 AVDD3 3 58 AVDD2 DAC13P 4 57 DAC4N DAC13N 5 56 DAC4P DAC14P 6 55 DAC3N DAC14N 7 54 DAC3P DAC15P 8 53 DAC2N 52 DAC2P 51 DAC1N DAC16N 11 50 DAC1P AVDD4 12 49 AVDD1 AGND4 13 48 AGND1 PLLGND 14 47 PU/R
PAGE 11
Data Sheet ADAU1966 Pin No.
PAGE 12
ADAU1966 Pin No. 68 69 70 71 72 73 74 75 76 77 78 79 80 1 Type 1 O O O O O O O O O O O O GND Data Sheet Mnemonic DAC7P DAC7N DAC8P DAC8N DAC9P DAC9N DAC10P DAC10N DAC11P DAC11N DAC12P DAC12N AGND3 Description DAC7 Positive Output. DAC7 Negative Output. DAC8 Positive Output. DAC8 Negative Output. DAC9 Positive Output. DAC9 Negative Output. DAC10 Positive Output. DAC10 Negative Output. DAC11 Positive Output. DAC11 Negative Output. DAC12 Positive Output. DAC12 Negative Output. Analog Ground.
PAGE 13
Data Sheet ADAU1966 TYPICAL PERFORMANCE CHARACTERISTICS 0.05 0.20 0.04 0.15 0.03 0.10 MAGNITUDE (dB) MAGNITUDE (dB) 0.02 0.01 0 –0.01 0.05 0 –0.05 –0.02 –0.10 –0.03 –0.15 –0.04 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY (FACTORED TO fS) –0.20 0 –10 –20 –20 –30 –30 MAGNITUDE (dB) –10 –40 –50 –60 –80 –90 –90 –100 –100 0.4 0.5 0.6 0.7 0.8 0.30 0.35 0.40 1.0 –60 –70 0.3 0.25 –50 –80 FREQUENCY (FACTORED TO fS) 0.20 –40 –70 0.9 1.
PAGE 14
ADAU1966 Data Sheet APPLICATION CIRCUITS Typical application circuits are shown in Figure 8 to Figure 11. Recommended loop filters for DLRCLK and MCLKI/XTALI modes of the PLL reference are shown in Figure 8. Output filters for the DAC outputs are shown in Figure 9 and Figure 10, and an external regulator circuit is shown in Figure 11. DLRCLK MCLKI/XTALI LF LF 39nF 5.6nF 2.2nF 390pF 3.32kΩ PLLVDD 09434-008 562Ω PLLVDD Figure 8.
PAGE 15
Data Sheet ADAU1966 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTERS (DACS) The 16 ADAU1966 digital-to-analog converter (DAC) channels are differential for improved noise and distortion performance and are voltage output for simplified connection. The DACs include on-chip digital interpolation filters with 68 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 256× (48 kHz range), 128× (96 kHz range), or 64× (192 kHz range).
PAGE 16
ADAU1966 Data Sheet After the PU/RST pin has been asserted high, the PLL_CLK_ CTRLx registers (Register 0x00 and Register 0x01) can be programmed. The on-chip phase-locked loop (PLL) can be selected to use the clock appearing at the MCLKI/XTALI pin at a frequency of 256, 384, 512, or 768 times the sample rate (fS), referenced to the 48 kHz mode from the master clock select (MCS) setting, as described in Table 12.
PAGE 17
Data Sheet ADAU1966 Table 12. MCS and fS Modes Master Clock Select (MCS), PLL_CLK_CTRL0[2:1] Setting 0, b00 Setting 1, b01 Setting 2, b10 Ratio MCLK (MHz) Ratio MCLK Ratio MCLK 256 × fS 8.192 384 × fS 12.288 512 × fS 16.384 256 × fS 11.2896 384 × fS 16.9344 512 × fS 22.5792 256 × fS 12.288 384 × fS 18.432 512 × fS 24.576 128 × fS 8.192 192 × fS 12.288 256 × fS 16.384 128 × fS 11.2896 192 × fS 16.9344 256 × fS 22.5792 128 × fS 12.288 192 × fS 18.432 256 × fS 24.576 64 × fS 8.192 96 × fS 12.288 128 × fS 16.
PAGE 18
ADAU1966 Data Sheet SCL SDA AD1 AD0 0 0 1 0 0 0 R/W START BY MASTER (S) 0 0 0 0 1 1 0 ACK. BY ADAU1966 (AS) ACK. BY ADAU1966 (AS) FRAME 2 REGISTER ADDRESS BYTE FRAME 1 CHIP ADDRESS BYTE SCL (CONTINUED) D7 D5 D6 D4 D3 D2 D1 D0 ACK. BY STOP BY ADAU1966 (AS) MASTER (P) FRAME 3 DATA BYTE TO ADAU1966 09434-012 SDA (CONTINUED) Figure 12. I2C Write Format SCL SDA AD1 AD0 0 0 1 0 0 R/W 0 0 0 0 0 1 1 0 ACK. BY ADAU1966 (AS) START BY MASTER (S) ACK.
PAGE 19
Data Sheet ADAU1966 SERIAL CONTROL PORT: SPI CONTROL MODE Table 21. SPI Address and R/W Byte Format The ADAU1966 has an SPI control port that permits programming and readback of the internal control registers for the DACs and clock system. A standalone mode is also available for operation without serial control; it is configured at reset using the SA_MODE pin. See the Standalone Mode section for details about SA_MODE.
PAGE 20
ADAU1966 Data Sheet tCLS tCLH tCCH tCCL tCCP CLATCH tCOTS CCLK tCDS tCDH COUT D23 D22 D9 tCOE D9 D8 D0 D8 D0 09434-117 CDATA tCOD Figure 17. Format of the SPI Signal POWER SUPPLY AND VOLTAGE REFERENCE SERIAL DATA PORTS—DATA FORMAT The ADAU1966 is designed for 5 V analog and 2.5 V digital supplies. To minimize noise pickup, bypass the power supply pins with 100 nF ceramic chip capacitors placed as close to the pins as possible.
PAGE 21
Data Sheet ADAU1966 Once a temperature conversion is placed in the THRM_TEMP_STAT register, the data can be translated into degrees Celsius (°C) using the following steps: mode. In one-shot mode, writing a 0 followed by writing a 1 to Bit 4, THRM_GO, results in a single reset and temperature conversion, placing the resulting temperature data in the THRM_TEMP_STAT register. In continuous operation mode, the data conversion takes place at a rate set by Bits[7:6], THRM_ RATE, with a range of 0.
PAGE 22
ADAU1966 Data Sheet Table 22.
PAGE 23
Data Sheet ADAU1966 DLRCLK 32 BITS INTERNAL DBCLK DSDATAx DLRCLK 09434-017 INTERNAL DBCLK TDM-DSDATAx Figure 20. Serial DAC Data Transmission in TDM Format Without DBCLK (Applicable Only If PLL Locks to DLRCLK) DLRCLK DATA MUST BE VALID AT THIS BCLK EDGE DSDATAx MSB Figure 21. Inverted DBCLK Mode in DAC Serial Data Transmission (Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission) Rev.
PAGE 24
ADAU1966 Data Sheet REGISTER SUMMARY Table 23.
PAGE 25
Data Sheet ADAU1966 REGISTER DETAILS PLL AND CLOCK CONTROL 0 REGISTER Address: 0x00, Reset: 0x00, Name: PLL_CLK_CTRL0 Table 24. Bit Descriptions for PLL_CLK_CTRL0 Bits [7:6] Bit Name PLLIN Settings 00 01 10 11 [5:4] XTAL_SET 00 01 10 11 3 SOFT_RST 0 1 [2:1] MCS 00 01 10 11 0 PUP 0 1 Description PLL Input Select. Selects between MCLKI/XTALI or DLRCLK as the input to the PLL. MCLKI or XTALI DLRCLK Reserved Reserved XTAL Oscillator Setting. XTALO pin status.
PAGE 26
ADAU1966 Data Sheet PLL AND CLOCK CONTROL 1 REGISTER Address: 0x01, Reset: 0x2A, Name: PLL_CLK_CTRL1 B7 B6 B5 B4 B3 B2 B1 B0 0 0 1 0 1 0 1 0 [7:6] LOPWR_MODE [0] CLK_SEL Global Power/Performance Adjust DAC Clock Select 00: I2C Register Settings 01: Reserved 10: Lower Power 11: Lowest Power 0: MCLK from PLL 1: MCLK from MCLKI or XTALI [1] VREF_EN Internal Voltage Reference Enable 0: Disabled 1: Enabled [5:4] MCLKO_SEL MCLK Output Frequency 00: MCLKO 01: MCLKO 10: MCLKO 11: MCLKO = 4
PAGE 27
Data Sheet ADAU1966 BLOCK POWER-DOWN AND THERMAL SENSOR CONTROL 1 REGISTER Address: 0x02, Reset: 0xA0, Name: PDN_THRMSENS_CTRL_1 Table 26. Bit Descriptions for PDN_THRMSENS_CTRL_1 Bits [7:6] Bit Name THRM_RATE Settings 00 01 10 11 5 THRM_MODE 0 1 4 THRM_GO 0 1 2 TS_PDN 0 1 1 PLL_PDN 0 1 0 VREG_PDN 0 1 Description Conversion Time Interval. When THERM_MODE = 0, the THERM_RATE bits control the time interval between temperature conversions. 4 sec/Conversion 0.
PAGE 28
ADAU1966 Data Sheet POWER-DOWN CONTROL 2 REGISTER Address: 0x03, Reset: 0x00, Name: PDN_CTRL2 Table 27. Bit Descriptions for PDN_CTRL2 Bits 7 Bit Name DAC08_PDN Settings 0 1 6 DAC07_PDN 0 1 5 DAC06_PDN 0 1 4 DAC05_PDN 0 1 3 DAC04_PDN 0 1 2 DAC03_PDN 0 1 1 DAC02_PDN 0 1 0 DAC01_PDN 0 1 Description Channel 8 Power-Down. Normal Operation Power-Down Channel 8 Channel 7 Power-Down. Normal Operation Power-Down Channel 7 Channel 6 Power-Down.
PAGE 29
Data Sheet ADAU1966 POWER-DOWN CONTROL 3 REGISTER Address: 0x04, Reset: 0x00, Name: PDN_CTRL3 Table 28. Bit Descriptions for PDN_CTRL3 Bits 7 Bit Name DAC16_PDN Settings 0 1 6 DAC15_PDN 0 1 5 DAC14_PDN 0 1 4 DAC13_PDN 0 1 3 DAC12_PDN 0 1 2 DAC11_PDN 0 1 1 DAC10_PDN 0 1 0 DAC09_PDN 0 1 Description Channel 16 Power-Down. Normal Operation Power-Down Channel 16 Channel 15 Power-Down. Normal Operation Power-Down Channel 15 Channel 14 Power-Down.
PAGE 30
ADAU1966 Data Sheet THERMAL SENSOR TEMPERATURE READOUT REGISTER Address: 0x05, Reset: 0x00, Name: THRM_TEMP_STAT Thermal Sensor Temperature Readout. −60°C to +140°C range, 1°C step size. Read this register and convert the hexadecimal or binary TEMP value into decimal form; then subtract 60 from this decimal conversion. The result is the temperature in degrees Celsius. Table 29. Bit Descriptions for THRM_TEMP_STAT Bits [7:0] Bit Name TEMP Settings Description Thermal Sensor Temperature Readout.
PAGE 31
Data Sheet ADAU1966 DAC CONTROL 0 REGISTER Address: 0x06, Reset: 0x01, Name: DAC_CTRL0 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 1 [7:6] SDATA_FMT [0] MMUTE SDATA Format DAC Master Mute 00: I2S—1-BCLK Cycle Delay 01: Left-Justified—0-BCLK Cycle Delay 10: Right-Justified 24-bit Data— 8-BCLK Cycle Delay 11: Right-Justified 16-bit Data— 16-BCLK Cycle Delay 0: Normal Operation 1: All Channels Muted [2:1] FS Sample Rate Select [5:3] SAI 00: 32 kHz/44.
PAGE 32
ADAU1966 Data Sheet DAC CONTROL 1 REGISTER Address: 0x07, Reset: 0x00, Name: DAC_CTRL1 Table 31. Bit Descriptions for DAC_CTRL1 Bits 7 Bit Name BCLK_GEN Settings 0 1 6 LRCLK_MODE 0 1 5 LRCLK_POL 0 1 4 SAI_MSB 0 1 2 BCLK_RATE 0 1 1 BCLK_EDGE 0 1 0 SAI_MS 0 1 Description DBCLK Generation. When the PLL is locked to DLRCLK, it is possible to run the ADAU1966 without an external DBCLK. Normal Operation—DBCLK Internal DBCLK Generation DLRCLK Mode Select. Only Valid for TDM modes.
PAGE 33
Data Sheet ADAU1966 DAC CONTROL 2 REGISTER Address: 0x08, Reset: 0x06, Name: DAC_CTRL2 Table 32. Bit Descriptions for DAC_CTRL2 Bits [6:5] Bit Name VREG_CTRL Settings 00 01 10 11 4 BCLK_TDMC 0 1 3 DAC_POL 0 1 2 AUTO_MUTE_EN 0 1 1 DAC_OSR 0 1 0 DE_EMP_EN 0 1 Description Voltage Regulator Control. Select the Regulator Output Voltage. Regulator Out = 2.5 V Regulator Out = 2.75 V Regulator Out = 3.0 V Regulator Out = 3.3 V DBCLK Rate in TDM Mode.
PAGE 34
ADAU1966 Data Sheet DAC INDIVIDUAL CHANNEL MUTES 1 REGISTER Address: 0x09, Reset: 0x00, Name: DAC_MUTE1 Table 33. Bit Descriptions for DAC_MUTE1 Bits 7 Bit Name DAC08_MUTE Settings 0 1 6 DAC07_MUTE 0 1 5 DAC06_MUTE 0 1 4 DAC05_MUTE 0 1 3 DAC04_MUTE 0 1 2 DAC03_MUTE 0 1 1 DAC02_MUTE 0 1 0 DAC01_MUTE 0 1 Description DAC8 Soft Mute. DAC8 Normal Operation DAC8 Mute DAC7 Soft Mute. DAC7 Normal Operation DAC7 Mute DAC6 Soft Mute. DAC6 Normal Operation DAC6 Mute DAC5 Soft Mute.
PAGE 35
Data Sheet ADAU1966 DAC INDIVIDUAL CHANNEL MUTES 2 REGISTER Address: 0x0A, Reset: 0x00, Name: DAC_MUTE2 Table 34. Bit Descriptions for DAC_MUTE2 Bits 7 Bit Name DAC16_MUTE Settings 0 1 6 DAC15_MUTE 0 1 5 DAC14_MUTE 0 1 4 DAC13_MUTE 0 1 3 DAC12_MUTE 0 1 2 DAC11_MUTE 0 1 1 DAC10_MUTE 0 1 0 DAC09_MUTE 0 1 Description DAC16 Soft Mute. DAC16 Normal Operation DAC16 Mute DAC15 Soft Mute. DAC15 Normal Operation DAC15 Mute DAC14 Soft Mute. DAC14 Normal Operation DAC14 Mute DAC13 Soft Mute.
PAGE 36
ADAU1966 Data Sheet MASTER VOLUME CONTROL REGISTER Address: 0x0B, Reset: 0x00, Name: DACMSTR_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 57 for a complete list of the volume settings. Table 35. Bit Descriptions for DACMSTR_VOL Bits [7:0] Bit Name DACMSTR_VOL Settings 00000000 00000001 00000010 11111110 11111111 Description Master Volume Control. 0 dB (default) −0.375 dB −0.750 dB −95.250 dB −95.
PAGE 37
Data Sheet ADAU1966 DAC 2 VOLUME CONTROL REGISTER Address: 0x0D, Reset: 0x00, Name: DAC02_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 57 for a complete list of the volume settings. Table 37. Bit Descriptions for DAC02_VOL Bits [7:0] Bit Name DAC02_VOL Settings 00000000 00000001 00000010 11111110 11111111 Description DAC Volume Control Channel 2. 0 dB (default) −0.375 dB −0.750 dB −95.250 dB −95.
PAGE 38
ADAU1966 Data Sheet DAC 4 VOLUME CONTROL REGISTER Address: 0x0F, Reset: 0x00, Name: DAC04_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 57 for a complete list of the volume settings. Table 39. Bit Descriptions for DAC04_VOL Bits [7:0] Bit Name DAC04_VOL Settings 00000000 00000001 00000010 11111110 11111111 Description DAC Volume Control Channel 4. 0 dB (default) −0.375 dB −0.750 dB −95.250 dB −95.
PAGE 39
Data Sheet ADAU1966 DAC 6 VOLUME CONTROL REGISTER Address: 0x11, Reset: 0x00, Name: DAC06_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 57 for a complete list of the volume settings. Table 41. Bit Descriptions for DAC06_VOL Bits [7:0] Bit Name DAC06_VOL Settings 00000000 00000001 00000010 11111110 11111111 Description DAC Volume Control Channel 6. 0 dB (default) −0.375 dB −0.750 dB −95.250 dB −95.
PAGE 40
ADAU1966 Data Sheet DAC 8 VOLUME CONTROL REGISTER Address: 0x13, Reset: 0x00, Name: DAC08_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 57 for a complete list of the volume settings. Table 43. Bit Descriptions for DAC08_VOL Bits [7:0] Bit Name DAC08_VOL Settings 00000000 00000001 00000010 11111110 11111111 Description DAC Volume Control Channel 8. 0 dB (default) −0.375 dB −0.750 dB −95.250 dB −95.
PAGE 41
Data Sheet ADAU1966 DAC 10 VOLUME CONTROL REGISTER Address: 0x15, Reset: 0x00, Name: DAC10_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 57 for a complete list of the volume settings. Table 45. Bit Descriptions for DAC10_VOL Bits [7:0] Bit Name DAC10_VOL Settings 00000000 00000001 00000010 11111110 11111111 Description DAC Volume Control Channel 10. 0 dB (default) −0.375 dB −0.750 dB −95.250 dB −95.
PAGE 42
ADAU1966 Data Sheet DAC 12 VOLUME CONTROL REGISTER Address: 0x17, Reset: 0x00, Name: DAC12_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 57 for a complete list of the volume settings. Table 47. Bit Descriptions for DAC12_VOL Bits [7:0] Bit Name DAC12_VOL Settings 00000000 00000001 00000010 11111110 11111111 Description DAC Volume Control Channel 12. 0 dB (default) −0.375 dB −0.750 dB −95.250 dB −95.
PAGE 43
Data Sheet ADAU1966 DAC 14 VOLUME CONTROL REGISTER Address: 0x19, Reset: 0x00, Name: DAC14_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 57 for a complete list of the volume settings. Table 49. Bit Descriptions for DAC14_VOL Bits [7:0] Bit Name DAC14_VOL Settings 00000000 00000001 00000010 11111110 11111111 Description DAC Volume Control Channel 14. 0 dB (default) −0.375 dB −0.750 dB −95.250 dB −95.
PAGE 44
ADAU1966 Data Sheet DAC 16 VOLUME CONTROL REGISTER Address: 0x1B, Reset: 0x00, Name: DAC16_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 57 for a complete list of the volume settings. Table 51. Bit Descriptions for DAC16_VOL Bits [7:0] Bit Name DAC16_VOL Settings 00000000 00000001 00000010 11111110 11111111 Description DAC Volume Control Channel 16. 0 dB (default) −0.375 dB −0.750 dB −95.250 dB −95.
PAGE 45
Data Sheet ADAU1966 DAC POWER ADJUST 1 REGISTER Address: 0x1D, Reset: 0xAA, Name: DAC_POWER1 Table 53. Bit Descriptions for DAC_POWER1 Bits [7:6] Bit Name DAC04_POWER Settings 00 01 10 11 [5:4] DAC03_POWER 00 01 10 11 [3:2] DAC02_POWER 00 01 10 11 [1:0] DAC01_POWER 00 01 10 11 Description DAC Power Control Channel 4. Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 3. Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 2.
PAGE 46
ADAU1966 Data Sheet DAC POWER ADJUST 2 REGISTER Address: 0x1E, Reset: 0xAA, Name: DAC_POWER2 Table 54. Bit Descriptions for DAC_POWER2 Bits [7:6] Bit Name DAC08_POWER Settings 00 01 10 11 [5:4] DAC07_POWER 00 01 10 11 [3:2] DAC06_POWER 00 01 10 11 [1:0] DAC05_POWER 00 01 10 11 Description DAC Power Control Channel 8. Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 7. Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 6.
PAGE 47
Data Sheet ADAU1966 DAC POWER ADJUST 3 REGISTER Address: 0x1F, Reset: 0xAA, Name: DAC_POWER3 Table 55. Bit Descriptions for DAC_POWER3 Bits [7:6] Bit Name DAC12_POWER Settings 00 01 10 11 [5:4] DAC11_POWER 00 01 10 11 [3:2] DAC10_POWER 00 01 10 11 [1:0] DAC09_POWER 00 01 10 11 Description DAC Power Control Channel 12. Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 11. Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 10.
PAGE 48
ADAU1966 Data Sheet DAC POWER ADJUST 4 REGISTER Address: 0x20, Reset: 0xAA, Name: DAC_POWER4 Table 56. Bit Descriptions for DAC_POWER4 Bits [7:6] Bit Name DAC16_POWER Settings 00 01 10 11 [5:4] DAC15_POWER 00 01 10 11 [3:2] DAC14_POWER 00 01 10 11 [1:0] DAC13_POWER 00 01 10 11 Description DAC Power Control Channel 16. Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 15. Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 14.
PAGE 49
Data Sheet ADAU1966 Table 57. Volume Table Binary Value Volume Attenuation (dB) Binary Value Volume Attenuation (dB) 00000000 0 00101110 −17.25 00000001 −0.375 00101111 −17.625 00000010 −0.75 00110000 −18 00000011 −1.125 00110001 −18.375 00000100 −1.5 00110010 −18.75 00000101 −1.875 00110011 −19.125 00000110 −2.25 00110100 −19.5 00000111 −2.625 00110101 −19.875 00001000 −3 00110110 −20.25 00001001 −3.375 00110111 −20.625 00001010 −3.
PAGE 50
ADAU1966 Data Sheet Binary Value Volume Attenuation (dB) Binary Value Volume Attenuation (dB) 01011100 −34.5 10001011 −52.125 01011101 −34.875 10001100 −52.5 01011110 −35.25 10001101 −52.875 01011111 −35.625 10001110 −53.25 01100000 −36 10001111 −53.625 01100001 −36.375 10010000 −54 01100010 −36.75 10010001 −54.375 01100011 −37.125 10010010 −54.75 01100100 −37.5 10010011 −55.125 01100101 −37.875 10010100 −55.5 01100110 −38.25 10010101 −55.875 01100111 −38.
PAGE 51
Data Sheet ADAU1966 Binary Value Volume Attenuation (dB) Binary Value Volume Attenuation (dB) 10111010 −69.75 11011101 −82.875 10111011 −70.125 11011110 −83.25 10111100 −70.5 11011111 −83.625 10111101 −70.875 11100000 −84 10111110 −71.25 11100001 −84.375 10111111 −71.625 11100010 −84.75 11000000 −72 11100011 −85.125 11000001 −72.375 11100100 −85.5 11000010 −72.75 11100101 −85.875 11000011 −73.125 11100110 −86.25 11000100 −73.5 11100111 −86.625 11000101 −73.
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ADAU1966 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 16.20 16.00 SQ 15.80 1.60 MAX 61 80 60 1 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.10 COPLANARITY VIEW A 20 41 40 21 VIEW A 0.65 BSC LEAD PITCH ROTATED 90° CCW 0.38 0.32 0.22 COMPLIANT TO JEDEC STANDARDS MS-026-BEC 051706-A 1.45 1.40 1.35 Figure 22.