Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADCLK944BCPZ-R2

2.5 V/3.3 V, Four LVPECL Outputs,

SiGe Clock Fanout Buffer

ADCLK944

Rev. 0

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FEATURES FEATURES

Operating frequency: 7.0 GHz Operating frequency: 7.0 GHz

Broadband random jitter: 50 fs rms Broadband random jitter: 50 fs rms

On-chip input terminations On-chip input terminations

Power supply (V

− V

): 2.5 V to 3.3 V Power supply (V

− V

): 2.5 V to 3.3 V

APPLICATIONS APPLICATIONS

Low jitter clock distribution Low jitter clock distribution

Clock and data signal restoration Clock and data signal restoration

Level translation Level translation

Wireless communications Wireless communications

Wired communications Wired communications

Medical and industrial imaging Medical and industrial imaging

ATE and high performance instrumentation ATE and high performance instrumentation

FUNCTIONAL BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM

LVPECL

ADCLK944

REFERENCE

REF

CLK

8770-001

Figure 1.

GENERAL DESCRIPTION

The ADCLK944 is an ultrafast clock fanout buffer fabricated on

the Analog Devices, Inc., proprietary XFCB3 silicon germanium

(SiGe) bipolar process. This device is designed for high speed

applications requiring low jitter.

The device has a differential input equipped with center-tapped,

differential, 100 Ω on-chip termination resistors. The input can

accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),

and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A V

REF

pin is available for biasing ac-coupled inputs.

The ADCLK944 features four full-swing emitter-coupled logic

(ECL) output drivers. For LVPECL (positive ECL) operation,

bias V

to the positive supply and V

to ground. For ECL

operation, bias V

to ground and V

to the negative supply.

The ECL output stages are designed to directly drive 800 mV

each side into 50 Ω terminated to V

− 2 V for a total differen-

tial output swing of 1.6 V.

The ADCLK944 is available in a 16-lead LFCSP and is specified

for operation over the standard industrial temperature range of

−40°C to +85°C.

Summary of content (12 pages)

PAGE 1
2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK944 FEATURES Operating frequency: 7.0 GHz Broadband random jitter: 50 fs rms On-chip input terminations Power supply (VCC − VEE): 2.5 V to 3.
PAGE 2
ADCLK944 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications ....................................................................................... 1 Thermal Performance ...................................................................5 Functional Block Diagram ..............................................................
PAGE 3
ADCLK944 SPECIFICATIONS Typical values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum and maximum values are given for the full VCC − VEE = 3.3 V + 10% to 2.5 V − 5% and TA = −40°C to +85°C variation, unless otherwise noted. CLOCK INPUTS AND OUTPUTS Table 1.
PAGE 4
ADCLK944 POWER Table 3. Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2 1 2 Symbol Min VCC − VEE 2.375 IVEE IVEE IVCC IVCC PSRVCC PSRVCC Typ 35 37 139 138 −3 28 Change in tPD per change in VCC. Change in output swing per change in VCC. Rev. 0 | Page 4 of 12 Max Unit Test Conditions/Comments 3.63 V 3.3 V + 10% to 2.5 V − 5% Static VCC − VEE = 2.5 V ± 5% VCC − VEE = 3.
PAGE 5
ADCLK944 ABSOLUTE MAXIMUM RATINGS DETERMINING JUNCTION TEMPERATURE Table 4.
PAGE 6
ADCLK944 13 VCC 14 Q0 15 Q0 16 VEE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK 1 12 Q1 VT 2 ADCLK944 11 Q1 VREF 3 TOP VIEW (Not to Scale) 10 Q2 CLK 4 NOTES 1. EXPOSED PAD MUST BE CONNECTED TO VEE. 08770-002 VCC 8 Q3 7 Q3 6 VEE 5 9 Q2 Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5, 16 6, 7 8, 13 9, 10 11, 12 14, 15 Mnemonic CLK VT VREF CLK VEE Q3, Q3 VCC Q2, Q2 Q1, Q1 Q0, Q0 EPAD Description Differential Input (Positive). Center Tap.
PAGE 7
ADCLK944 TYPICAL PERFORMANCE CHARACTERISTICS VCC = 3.3 V, VEE = 0.0 V, VICM = VREF, TA = 25°C, clock outputs terminated at 50 Ω to VCC − 2 V, unless otherwise noted. CH1 300mV M 1.25ns 20.0GS/s A CH1 36.0mV IT 25.0ps/pt CH1 300mV Figure 3. LVPECL Differential Output Waveform at 200 MHz 1.55 1.4 3.3V 1.2 2.5V 1.0 0.8 0.6 0.4 0 1000 2000 3000 4000 5000 6000 7000 8000 FREQUENCY (MHz) Figure 4. Differential Output Voltage Swing vs. Frequency –40°C 1.45 1.40 1.35 1.30 2.2 2.4 2.6 2.8 3.
PAGE 8
ADCLK944 160 300 140 250 –40°C +25°C +85°C 100 80 60 40 IVEE 2.625 2.970 3.300 3.630 POWER SUPPLY VOLTAGE (V) 0 –90 –110 –120 –130 ADCLK944 –150 –170 10 CLOCK SOURCE 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M 08770-011 PHASE NOISE (dBc/Hz) –100 –140 5 10 15 INPUT SLEW RATE (V/ns) Figure 9. Power Supply Current vs. Power Supply Voltage and Temperature, All Outputs Loaded (50 Ω to VCC − 2 V) –160 100 0 08770-010 0 2.500 150 50 20 2.375 200 Figure 10.
PAGE 9
ADCLK944 THEORY OF OPERATION The ADCLK944 accepts a differential clock input and distributes it to all four LVPECL outputs. The maximum specified frequency is the point at which the output voltage swing is 50% of the standard LVPECL swing (see Figure 4). The device has a differential input equipped with center-tapped, differential, 100 Ω on-chip termination resistors. The input can accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended, 3.3 V operation only), and ac-coupled 1.
PAGE 10
ADCLK944 The ADCLK944 buffer is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes for both the negative supply (VEE) and the positive supply (VCC) planes as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application.
PAGE 11
ADCLK944 INPUT TERMINATION OPTIONS VCC VREF VREF VT VT 50Ω CLK 50Ω 50Ω CLK CLK 50Ω CONNECT VT TO VCC. 08770-021 08770-019 CLK CONNECT VT TO VREF . Figure 20. AC Coupling Differential Signal Inputs, Such as LVDS Figure 18. Interfacing to CML Inputs VREF VT VREF 50Ω CLK VT VCC – 2V 50Ω CLK 50Ω 50Ω CLK 08770-020 CONNECT VT TO VCC − 2V. CONNECT VT, VREF , AND CLK TOGETHER. PLACE A BYPASS CAPACITOR FROM VT TO GROUND.
PAGE 12
ADCLK944 OUTLINE DIMENSIONS PIN 1 INDICATOR 3.10 3.00 SQ 2.90 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 16 13 1 12 EXPOSED PAD 1.60 1.50 SQ 1.40 9 0.80 0.75 0.70 4 8 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 111808-A TOP VIEW 0.45 0.40 0.35 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 22.