Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADCLK948BCPZ

Two Selectable Inputs, 8 LVPECL Outputs,

SiGe Clock Fanout Buffer

ADCLK948

Rev. A

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FEATURES FEATURES

2 selectable differential inputs 2 selectable differential inputs

4.8 GHz operating frequency 4.8 GHz operating frequency

75 fs rms broadband random jitter 75 fs rms broadband random jitter

On-chip input terminations On-chip input terminations

3.3 V power supply 3.3 V power supply

APPLICATIONS APPLICATIONS

Low jitter clock distribution Low jitter clock distribution

Clock and data signal restoration Clock and data signal restoration

Level translation Level translation

Wireless communications Wireless communications

Wired communications Wired communications

Medical and industrial imaging Medical and industrial imaging

ATE and high performance instrumentation ATE and high performance instrumentation

GENERAL DESCRIPTION GENERAL DESCRIPTION

The ADCLK948 is an ultrafast clock fanout buffer fabricated

on the Analog Devices, Inc., proprietary XFCB3 silicon germanium

(SiGe) bipolar process. This device is designed for high speed

applications requiring low jitter.

The ADCLK948 is an ultrafast clock fanout buffer fabricated

on the Analog Devices, Inc., proprietary XFCB3 silicon germanium

(SiGe) bipolar process. This device is designed for high speed

applications requiring low jitter.

The device has two selectable differential inputs via the IN_SEL

control pin. Both inputs are equipped with center tapped,

differential, 100 Ω on-chip termination resistors. The inputs

accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),

and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A

REF

x pin is available for biasing ac-coupled inputs.

The device has two selectable differential inputs via the IN_SEL

control pin. Both inputs are equipped with center tapped,

differential, 100 Ω on-chip termination resistors. The inputs

accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),

and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A

REF

x pin is available for biasing ac-coupled inputs.

The ADCLK948 features eight full-swing emitter coupled logic

(ECL) output drivers. For LVPECL (positive ECL) operation,

bias V

to the positive supply and V

to ground. For ECL

operation, bias V

to ground and V

to the negative supply.

The ADCLK948 features eight full-swing emitter coupled logic

(ECL) output drivers. For LVPECL (positive ECL) operation,

bias V

to the positive supply and V

to ground. For ECL

operation, bias V

to ground and V

to the negative supply.

The output stages are designed to directly drive 800 mV each

side into 50 Ω terminated to V

− 2 V for a total differential

output swing of 1.6 V.

The output stages are designed to directly drive 800 mV each

side into 50 Ω terminated to V

− 2 V for a total differential

output swing of 1.6 V.

The ADCLK948 is available in a 32-lead LFCSP and specified

for operation over the standard industrial temperature range of

−40°C to +85°C.

The ADCLK948 is available in a 32-lead LFCSP and specified

for operation over the standard industrial temperature range of

−40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM

REF

IN_SEL

CLK0

CLK1

LVPECL

ADCLK948

REFERENCE

08280-001

Figure 1.

Summary of content (12 pages)

PAGE 1
Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK948 FEATURES FUNCTIONAL BLOCK DIAGRAM 2 selectable differential inputs 4.8 GHz operating frequency 75 fs rms broadband random jitter On-chip input terminations 3.
PAGE 2
ADCLK948 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 General Description .........................................................................
PAGE 3
ADCLK948 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Typical (Typ column) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min column) and maximum (Max column) values are given over the full VCC − VEE = 3.3 V ± 10% and TA = −40°C to +85°C variation, unless otherwise noted. Table 1.
PAGE 4
ADCLK948 Table 3. Input Select Control Pin Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance Symbol VIH VIL IIH IIL Min VCC − 0.4 VEE Typ 2 Max VCC 1 100 0.6 Unit V V μA mA pF Table 4. Power Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2 1 2 Symbol Min VCC − VEE 2.
PAGE 5
ADCLK948 ABSOLUTE MAXIMUM RATINGS DETERMINING JUNCTION TEMPERATURE Table 5.
PAGE 6
ADCLK948 32 31 30 29 28 27 26 25 IN_SEL VCC Q0 Q0 Q1 Q1 VCC VCC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADCLK948 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 NOTES 1. NC = NO CONNECT. 2. EPAD MUST BE SOLDERED TO VEE POWER PLANE. 08280-002 NC VCC Q7 Q7 Q6 Q6 VCC VCC 9 10 11 12 13 14 15 16 CLK0 CLK0 VREF 0 VT0 CLK1 CLK1 VT1 VREF 1 Figure 2. Pin Configuration Table 7. Pin Function Descriptions Pin No.
PAGE 7
ADCLK948 TYPICAL PERFORMANCE CHARACTERISTICS VCC = 3.3 V, VEE = 0 V, VICM = VREFx, TA = 25°C, clock outputs terminated at 50 Ω to VCC − 2 V, unless otherwise noted. C4 C3 C4 C3 C4 500ps/DIV 100mV/DIV Figure 3. LVPECL Output Waveform @ 200 MHz 08280-006 C3 08280-003 100mV/DIV 100ps/DIV Figure 6. LVPECL Output Waveform @ 1000 MHz 1.8 214 213 1.6 1.5 PROPAGATION DELAY (ps) DIFFERENTIAL OUTPUT VOLTAGE (V) 1.7 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 212 211 210 209 208 0.
PAGE 8
ADCLK948 –90 ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672), WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D). –100 –40°C PHASE NOISE (dBc/Hz) 1.52 +25°C 1.50 +85°C 1.48 1.46 –110 –120 –130 ADCLK948 –140 –150 1.44 –160 1.42 2.75 –170 10 2.85 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 3.
PAGE 9
ADCLK948 FUNCTIONAL DESCRIPTION Output jitter performance is degraded by an input slew rate below 4 V/ns, as shown in Figure 12. The ADCLK948 is specifically designed to minimize added random jitter over a wide input slew rate range. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate. Input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics.
PAGE 10
ADCLK948 A Logic 0 on the IN_SEL pin selects the Input CLK0 and Input CLK0. A Logic 1 on the IN_SEL pin selects Input CLK1 and Input CLK1. PCB LAYOUT CONSIDERATIONS The ADCLK948 buffer is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes for both the negative supply (VEE) and the positive supply (VCC) planes as part of a multilayer board.
PAGE 11
ADCLK948 INPUT TERMINATION OPTIONS VREF x VREF x VTx VTx 50Ω CLKx 50Ω 50Ω CLKx CLKx 50Ω CLKx ADCLK948 08280-019 ADCLK948 CONNECT VTx TO VCC. 08280-021 VCC CONNECT VTx TO VREF x. Figure 19. DC-Coupled CML Input Termination Figure 21. AC-Coupled Input Termination, Such as LVDS and LEVPECL VREF x V Tx VCC 50Ω CLKx CLKx 50Ω ADCLK948 CONNECT VTx, VREF x, AND CLKx. PLACE A BYPASS CAPACITOR FROM VTx TO GROUND.
PAGE 12
ADCLK948 OUTLINE DIMENSIONS 5.00 BSC SQ TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 12° MAX 32 1 2.85 2.70 SQ 2.55 EXPOSED PAD (BOTTOM VIEW) 17 16 PIN 1 INDICATOR 9 8 0.20 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.25 0.18 25 24 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.