Datasheet

ADCLK950
Rev. A | Page 3 of 12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ column) values are given for V
CC
− V
EE
= 3.3 V and T
A
= 25°C, unless otherwise noted. Minimum (Min column) and maximum
(Max column) values are given over the full V
CC
− V
EE
= 3.3 V ± 10% and T
A
= −40°C to +85°C variation, unless otherwise noted.
Table 1. Clock Inputs and Outputs
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input Common Mode Voltage V
ICM
V
EE
+ 1.5 V
CC
− 0.1 V
Input Differential Range V
ID
0.4 3.4 V p-p ±1.7 V between input pins
Input Capacitance C
IN
0.4 pF
Input Resistance
Single-Ended Mode 50 Ω
Differential Mode 100 Ω
Common Mode 50 kΩ Open V
T
x
Input Bias Current 20 µA
Hysteresis 10 mV
DC OUTPUT CHARACTERISTICS
Output Voltage High Level V
OH
V
CC
− 1.26 V
CC
− 0.76 V 50 Ω to (V
CC
− 2.0 V)
Output Voltage Low Level V
OL
V
CC
− 1.99 V
CC
− 1.54 V 50 Ω to (V
CC
− 2.0 V)
Output Voltage, Single Ended V
O
610 960 mV V
OH
− V
OL
, output static
Reference Voltage V
REF
Output Voltage (V
CC
+ 1)/2 V −500 µA to +500 µA
Output Resistance 235 Ω
Table 2. Timing Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC PERFORMANCE
Maximum Output Frequency 4.5 4.8 GHz
See Figure 4 for differential output voltage vs.
frequency, >0.8 V differential output swing
Output Rise Time t
R
40 75 90 ps 20% to 80% measured differentially
Output Fall Time t
F
40 75 90 ps
Propagation Delay t
PD
175 210 245 ps V
ICM
= 2 V, V
ID
= 1.6 V p-p
Temperature Coefficient 50 fs/°C
Output-to-Output Skew
1
9 28 ps
Part-to-Part Skew 45 ps V
ID
= 1.6 V p-p
Additive Time Jitter
Integrated Random Jitter 28 fs rms BW = 12 kHz − 20 MHz, CLK = 1 GHz
Broadband Random Jitter
2
75 fs rms V
ID
= 1.6 V p-p, 8 V/ns, V
ICM
= 2 V
Crosstalk-Induced Jitter
3
90 fs rms
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise
Input slew rate > 1 V/ns (see Figure 11, the
phase noise plot, for more details)
f
IN
= 1 GHz −119 dBc/Hz @100 Hz offset
−134 dBc/Hz @1 kHz offset
−145 dBc/Hz @10 kHz offset
−150 dBc/Hz @100 kHz offset
−150 dBc/Hz >1 MHz offset
1
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
2
Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
3
This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.