Datasheet

Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 101 of 156
Table 92. LCD Configuration X SFR (LCDCONX, Address 0x9C)
Bit Mnemonic Default Description
7 Reserved 0 Reserved.
6 EXTRES 0 External resistor ladder selection bit.
EXTRES Result
0 External resistor ladder is disabled. Charge pump is enabled
1 External resistor ladder is enabled. Charge pump is disabled
[5:0] BIASLVL 0 Bias level selection bits (see Table 93).
Table 93. LCD Bias Voltage When Contrast Control Is Enabled
BIASLVL[5] V
A
(V)
1/2 Bias 1/3 Bias
V
B
V
C
V
B
V
C
0
[ ]
31
4:0BIASLVL
V
REF
×
V
B
= V
A
V
C
= 2 × V
A
V
B
= 2 × V
A
V
C
= 3 × V
A
1
[ ]






+×
31
1
4:0BIASLVL
V
REF
V
B
= V
A
V
C
= 2 × V
A
V
B
= 2 × V
A
V
C
= 3 × V
A
Table 94. LCD Configuration Y SFR (LCDCONY, Address 0xB1)
Bit Mnemonic Default Description
7 AUTOSCREENSCROLL 0 When set, the four screens scroll automatically. The scrolling item is selected
by the BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96[5:4]). If both
BLINKEN in the LCD configuration SFR (LCDCON, Address 0x95[5]) and
AUTOSCREENSCROLL are set, this bit preempts the blinking mode.
6 INV_LVL 0 Frame inversion mode enable bit. If this bit is set, frames are inverted every other
frame. If this bit is cleared, frames are not inverted.
[5:4] Reserved 00 These bits should be kept cleared to 0 for proper operation.
[3:2] SCREEN_SEL 00 These bits select the screen that is being output on the LCD pins. Values of 0, 1, 2,
and 3 select Screen 0, Screen 1, Screen 2, and Screen 3, respectively.
1 UPDATEOVER 0 Update finished flag bit. This bit is updated by the LCD driver. When set, this bit
indicates that the LCD memory has been updated and a new frame has begun.
0 REFRESH 0 Refresh LCD data memory bit. This bit should be set by the user. When set, the
LCD driver does not use the data in the LCD data registers to update the display.
The LCD data registers can be updated by the 8052. When cleared, the LCD driver
uses the data in the LCD data registers to update the display at the next frame.
Table 95. LCD Clock SFR (LCDCLK, Address 0x96)
Bit Mnemonic Default Description
[7:6] BLKMOD 00 Blink mode clock source configuration bits.
BLKMOD Result
00
The blink rate is controlled by software; the display is off
01 The blink rate is controlled by software; the display is on
10 The blink rate is 2 Hz
11 The blink rate is set by the BLKFREQ bits
[5:4] BLKFREQ 00 Blink rate configuration bits. These bits control the LCD blink rate if BLKMOD (Bits[7:6]) = 11.
BLKFREQ Result (Blink Rate)
00 1 Hz
01 1/2 Hz
10 1/3 Hz
11 1/4 Hz
[3:0] FD 0000 LCD frame rate selection bits (see Table 96 and Table 97).