Datasheet
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 104 of 156
BLINK MODE
Blink mode is enabled by setting the BLINKEN bit (Bit 5) in the
LCD configuration SFR (LCDCON, Address 0x95). This mode
is used to alternate between the LCD on state and LCD off state
so that the LCD screen appears to blink. There are two blink
modes: a software controlled blink mode and an automatic
blink mode.
Software Controlled Blink Mode
The LCD blink rate can be controlled by user code by toggling
the BLKMOD bits (Bits[7:6]) in the LCD clock SFR (LCDCLK,
Address 0x96) to turn the display on and off at a rate that is
determined by the MCU code.
Automatic Blink Mode
There are five blink rates. These blink rates are selected by the
BLKMOD bits (Bits[7:6]) and the BLKFREQ bits (Bits[5:4]) in
the LCD clock SFR (LCDCLK, Address 0x96); see Table 95.
SCROLLING MODE
The ADE5166/ADE5169/ADE5566/ADE5569 can store up to
four screens in memory. The LCD driver can use any of these
screens by setting the SCREEN_SEL bits (Bits[3:2]) in the LCD
Configuration Y SFR (LCDCONY, Address 0xB1) and clearing
the refresh bit (Bit 0) in the same register. The software scrolling
of the screens can then be achieved by a one-command instruction.
Automatic Scrolling Mode
The ADE5166/ADE5169/ADE5566/ADE5569 provide automatic
scrolling between the screens using the five available blink rates.
Setting the AUTOSCREENSCROLL bit (Bit 7) in the LCD Con-
figuration Y SFR (LCDCONY, Address 0xB1), as well as the
BLINKEN bit (Bit 5) in the LCD configuration SFR (LCDCON,
Address 0x95) enables this mode. To allow the scrolling frequency
to be selected, the BLKMOD bits (Bits[7:6]) in the LCD clock
SFR (LCDCLK, Address 0x96) should both be set to 1. The scrol-
ling rates are then selected by the BLKFREQ bits (Bits[5:4]) in
the LCD clock SFR (LCDCLK, Address 0x96); see Table 95.
Automatic scrolling mode is available in all operating modes.
DISPLAY ELEMENT CONTROL
Four banks of 15 bytes of data memory located in the LCD module
control the on or off state of each segment of the LCD. The LCD
data memory is stored in Address 0 through Address 14 in the
LCD module, with two extra bits defining which one of the four
screens is being addressed.
Each byte configures the on and off states of two segment lines.
The LSBs store the state of the even numbered segment lines,
and the MSBs store the state of the odd numbered segment lines.
For example, LCD Data Address 0 refers to segment Line 1 and
Line 0 (see Table 102). Note that the LCD data memory is
maintained in the PSM2 operating mode.
The LCD data memory is accessed indirectly through the LCD
pointer SFR (LCDPTR, Address 0xAC) and LCD data SFR
(LCDDAT, Address 0xAE). Moving a value to the LCDPTR SFR
selects the LCD screen and data byte to be accessed and initiates
a read or write operation (see Table 99).
Table 102. LCD Data Memory Accessed Indirectly Through LCD Pointer SFR (LCDPTR, Address 0xAC) and LCD Data SFR
(LCDDAT, Address 0xAE)
1,
2
LCD Pointer SFR (LCDPTR, Address 0xAC) LCD Data SFR (LCDDAT, Address 0xAE)
LCD Memory Address COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
0x0E FP28 FP28 FP28 FP28
0x0D
FP27
FP27
FP27
FP27
N/A
N/A
N/A
N/A
0x0C FP25 FP25 FP25 FP25 FP24 FP24 FP24 FP24
0x0B FP23 FP23 FP23 FP23 FP22 FP22 FP22 FP22
0x0A FP21 FP21 FP21 FP21 FP20 FP20 FP20 FP20
0x09 FP19 FP19 FP19 FP19 FP18 FP18 FP18 FP18
0x08
FP17
FP17
FP17
FP17
FP16
FP16
FP16
FP16
0x07 FP15 FP15 FP15 FP15 FP14 FP14 FP14 FP14
0x06 FP13 FP13 FP13 FP13 FP12 FP12 FP12 FP12
0x05 FP11 FP11 FP11 FP11 FP10 FP10 FP10 FP10
0x04 FP9 FP9 FP9 FP9 FP8 FP8 FP8 FP8
0x03 FP7 FP7 FP7 FP7 FP6 FP6 FP6 FP6
0x02 FP5 FP5 FP5 FP5 FP4 FP4 FP4 FP4
0x01 FP3 FP3 FP3 FP3 FP2 FP2 FP2 FP2
0x00 FP1 FP1 FP1 FP1 FP0 FP0 FP0 FP0
1
COMx designates the common lines.
2
FPx designates the segment lines.