Datasheet

Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 125 of 156
RTC REGISTERS
Table 134. RTC Register List
Address
RTCPTR[4:0]
Mnemonic R/W Length
Signed/
Unsigned
Default
Value
Description
0x00 Reserved N/A N/A N/A N/A Reserved.
0x01 HTHSEC R/W 8 U 0 Counter. Updates every 1/128 second, referenced from the
calibrated 32.768 kHz clock. It overflows from 127 to 00,
incrementing the seconds counter, SEC.
0x02 SEC R/W 8 U 0 Counter. Updates every second, referenced from the calibrated
32.768 kHz clock. It overflows from 59 to 00, incrementing the
minutes counter, MIN.
0x03 MIN R/W 8 U 0 Counter. Updates every minute, referenced from the calibrated
32.768 kHz clock. It overflows from 59 to 00, incrementing the
hours counter, HOUR.
0x04 HOUR R/W 8 U 0 Counter. Updates every hour, referenced from the calibrated
32.768 kHz clock. It overflows from 23 to 00, incrementing the DAY
and DATE counters.
0x05 DAY R/W 8 U 0 Counter. Updates every day, referenced from the calibrated 32.768 kHz
clock. It overflows from 6 to 0.
0x06 DATE R/W 8 U 1 Counter. Updates every day, referenced from the calibrated 32.768 kHz
clock. It overflows from 28/29/30 or 31 to 01, depending on the month,
incrementing the month counter, MONTH.
0x07 MONTH R/W 8 U 1 Counter. Starts at 1 and updates every month, referenced from the
calibrated 32.768 kHz clock. It overflows from 12 to 01, incrementing
the year counter, YEAR.
0x08 YEAR R/W 8 U 0 Counter. Updates every year, referenced from the calibrated
32.768 kHz clock.
0x09 INTVAL R/W 8 U 0 Interval timer. Counts according to the timebase established in the
ITS bits of the RTC configuration SFR (TIMECON, Address 0xA1[5:4]).
When the number of counts is equal to INTVAL, ITFLAG (TIMECON[2])
is set, and a pending RTC interrupt is created, if enabled. Note that
the interval counter is eight bits, so it could count up to 255 sec, for
example.
0x0A AL_SEC R/W 8 U 0 Alarm second register. When this register matches the SEC register,
and the ALSEC_EN bit (TIMECON2, Address 0xA2[0]) is set, ALFLAG
(TIMECON[6]) is issued if all other enabled alarms match their
corresponding timekeeping register. If enabled, a pending RTC
interrupt is generated.
0x0B AL_MIN R/W 8 U 0 Alarm minute register. When this register matches the MIN register
and the ALMIN_EN bit (TIMECON2, Address 0xA2[1]) is set, ALFLAG
(TIMECON[6]) is issued if all other enabled alarms match their
corresponding timekeeping register. If enabled, a pending RTC
interrupt is generated.
0x0C AL_HOUR R/W 8 U 0 Alarm hour register. When this register matches the HOUR register
and the ALHR_EN bit (TIMECON2, Address 0xA2[2]) is set, ALFLAG
(TIMECON[6]) is issued if all other enabled alarms match their
corresponding timekeeping register. If enabled, a pending RTC
interrupt is generated.
0x0D AL_DAY R/W 8 U 0 Alarm day register. When this register matches the DAY register
and the ALDAY_EN bit (TIMECON2, Address 0xA2[3]) is set, ALFLAG
(TIMECON[6]) is issued if all other enabled alarms match their
corresponding timekeeping registers. If enabled, a pending RTC
interrupt is generated.
0x0E AL_DATE R/W 8 U 0 Alarm date register. When this register matches the DATE register
and the ALDAT_EN bit (TIMECON2, Address 0xA2[4]) is set, ALFLAG
(TIMECON[6]) is issued if all other enabled alarms match their
corresponding timekeeping registers. If enabled, a pending RTC
interrupt is generated.
0x0F
RTC_CAL
R/W
8
U
0
Configuration of the RTC calibration output (see Table 135).