Datasheet

Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 127 of 156
Table 137. Leap Years—Rollover After 29 Days
YEAR Register Estimated Year
0d04 2004
0d08 2008
0d12 2012
0d16 2016
0d20 2020
0d24 2024
0d28 2028
0d32 2032
0d36 2036
0d40
2040
0d44 2044
0d48 2048
0d52 2052
0d56 2056
0d60 2060
0d64 2064
0d68 2068
0d72 2072
0d76 2076
0d80 2080
0d84 2084
0d88 2088
0d92 2092
0d96 2096
RTC INTERRUPTS
The RTC alarm and interval timer interrupts are enabled by
setting the ETI bit in the Interrupt Enable and Priority 2 SFR
(IEIP2, Address 0xA9[2]). When an alarm or interval timer
event occurs, the corresponding flag is set and a pending RTC
interrupt is generated. If the RTC interrupt is enabled, the program
vectors to the RTC interrupt address, and the corresponding
RTC flag can be cleared in software. Moving to the RTC interrupt
address alone does not automatically clear the flag. To success-
fully acknowledge the interrupt event, the flag must be cleared
by software. If the RTC interrupt is disabled when the event occurs,
the pending interrupt remains until the corresponding RTC flag
is cleared. Therefore, the ALFLAG and ITFLAG flags (Bit 6 and
Bit 2, respectively, in the RTC configuration SFR (TIMECON,
Address 0xA1)) drive the RTC interrupt and should be managed
by the user to keep track of the RTC events.
Note that, if the ADE5166/ADE5169/ADE5566/ADE5569 are
awakened by an RTC event, either the ALFLAG or ITFLAG,
then the pending RTC interrupt, must be serviced before the
devices can go back to sleep again. The ADE5166/ADE5169/
ADE5566/ADE5569 keep waking up until this interrupt has
been serviced.
Interval Timer Alarm
The RTC can be used as an interval timer. When the interval timer
is enabled by setting ITEN (TIMECON[1]), the interval timer
clock source selected by the ITS1 and ITS0 bits (TIMECON[5:4]) is
passed through to an 8-bit counter. This counter increments on
every interval timer clock pulse until the 8-bit counter is equal to
the value in the alarm interval register. Then an alarm event is
generated, setting the ITFLAG bit (TIMECON[2]) and creating
a pending RTC interrupt. If the SIT bit (TIMECON[3]) is cleared,
the 8-bit counter is cleared and starts counting again. If the SIT
bit is set, the 8-bit counter is held in reset after the alarm occurs.
Take care when changing the interval timer timebase. The
recommended procedure is as follows:
1. If the INTVAL register is to be modified, write to the I NT VA L
register first. Then wait for one 128 Hz clock cycle to syn-
chronize with the RTC, 64,000 cycles at a 4.096 MHz
instruction cycle clock.
2. Disable the interval timer by clearing ITEN (TIMECON[1]).
Then wait for one 128 Hz clock cycle to synchronize with the
RTC, 64,000 cycles at a 4.096 MHz instruction cycle clock.
3. Read the TIMECON SFR to ensure that the ITEN bit is
cleared. If it is not, wait for another 128 Hz clock cycle.
4. Set the timebase bits, ITS1 and ITS0 (TIMECON[5:4]) to
configure the interval. Wait for a 128 Hz clock cycle for this
change to take effect.
RTC Wake-Up Alarm
The RTC can be used with an alarm to wake up periodically. The
alarm registers (AL_SEC, AL_MIN, AL_HOUR, AL_DAY, and
AL_DATE) should be set to the specific time that the alarm event
is required, and the corresponding ALxxx_EN bits must be set in
the RTC Configuration 2 SFR (TIMECON2, Address 0xA2). The
enabled alarm registers are then compared to their respective
RTC registers (SEC, MIN, HOUR, DAY, and DATE). When all
enabled alarms match their corresponding RTC registers, the alarm
flag is set, and a pending interrupt is generated. If the alarm flag
(ALFLAG, TIMECON[6]) is enabled, an RTC interrupt occurs
and the program vectors to the RTC interrupt address.