Datasheet

Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 129 of 156
UART SERIAL INTERFACE
The ADE5166/ADE5169/ADE5566/ADE5569 UART can be
configured in one of four modes.
• Shift register with baud rate fixed at f
CORE
/12
• 8-bit UART with variable baud rate
• 9-bit UART with baud rate fixed at f
CORE
/64 or f
CORE
/32
• 9-bit UART with variable baud rate
Variable baud rates are defined by using an internal timer to
generate any rate between 300 bauds/sec and 115,200 bauds/sec.
The UART serial interface provided in the ADE5166/ADE5169/
ADE5566/ADE5569 is a full-duplex serial interface. It is also
receive buffered by storing the first received byte in a receive buffer
until the reception of the second byte is complete. The physical
interface to the UART is provided via the RxD (P1.0/RxD) and
TxD (P1.1/TxD) pins, and the firmware interface is through the
SFRs, as presented in Table 139.
Both the serial port receive and transmit registers are accessed
through the serial port buffer SFR (SBUF, Address 0x99). Writing
to SBUF loads the transmit register, and reading SBUF accesses
a physically separate receive register.
An enhanced UART mode is offered by using the UART timer and
by providing enhanced frame error, break error, and overwrite
error detection. This mode is enabled by setting the EXTEN bit
in the configuration SFR (CFG, Address 0xAF[6]) (see the UART
Additional Features section). The enhanced serial baud rate control
SFR (SBAUDT, Address 0x9E) and UART timer fractional divider
SFR (SBAUDF, Address 0x9D) are used to configure the UART
timer and to indicate the enhanced UART errors.
UART SFRs
Table 139. Serial Port SFRs
SFR
Address
Bit Addressable
Description
SCON 0x98 Yes Serial communications control (see Table 140).
SBUF 0x99 No Serial port buffer (see Table 141).
SBAUDT 0x9E No Enhanced serial baud rate control (see Table 142).
SBAUDF 0x9D No UART timer fractional divider (see Table 143).
Table 140. Serial Communications Control SFR (SCON, Address 0x98)
Bit
Bit Address
Mnemonic
Default
Description
[7:6] 0x9F, 0x9E SM0, SM1 00 UART serial mode select bits. These bits select the serial port operating mode.
SM0, SM1
Result (Selected Operating Mode)
00
Mode 0, shift register, fixed baud rate (f
CORE
/12)
01 Mode 1, 8-bit UART, variable baud rate
10 Mode 2, 9-bit UART, fixed baud rate (f
CORE
/32) or (f
CORE
/16)
11 Mode 3, 9-bit UART, variable baud rate
5 0x9D SM2 0 Multiprocessor communication enable bit. Enables multiprocessor communication in
Mode 2 and Mode 3, and framing error detection in Mode 1.
In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received.
If SM2 is cleared, RI is set as soon as the byte of data is received.
In Mode 2 or Mode 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0.
If SM2 is cleared, RI is set as soon as the byte of data is received.
4 0x9C REN 0 Serial port receive enable bit. Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
3 0x9B TB8 0 Serial port transmit (Bit 9). The data loaded into TB8 is the ninth data bit transmitted in
Mode 2 and Mode 3.
2 0x9A RB8 0 Serial port receiver (Bit 9). The ninth data bit received in Mode 2 and Mode 3 is latched
into RB8. For Mode 1, the stop bit is latched into RB8.
1 0x99 TI 0 Serial port transmit interrupt flag. Set by hardware at the end of the eighth bit in Mode 0 or
at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3.
TI must be cleared by user software.
0 0x98 RI 0 Serial port receive interrupt flag. Set by hardware at the end of the eighth bit in Mode 0 or
halfway through the stop bit in Mode 1, Mode 2, and Mode 3.
RI must be cleared by user software.