Datasheet

ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 130 of 156
Table 141. Serial Port Buffer SFR (SBUF, Address 0x99)
Bit Mnemonic Default Description
[7:0] SBUF 0 Serial port data buffer.
Table 142. Enhanced Serial Baud Rate Control SFR (SBAUDT, Address 0x9E)
Bit Mnemonic Default Description
7 OWE 0 Overwrite error. This bit is set when new data is received and RI = 1 (Bit 0 in the SCON SFR, Address
0x98). It indicates that SBUF was not read before the next character was transferred in, causing the
prior SBUF data to be lost. Write a 0 to this bit to clear it.
6 FE 0 Frame error. This bit is set when the received frame does not have a valid stop bit. This bit is read
only and is updated every time a frame is received.
5 BE 0 Break error. This bit is set whenever the receive data line (Rx) is low for longer than a full transmission
frame, which is the time required for a start bit, eight data bits, a parity bit, and half a stop bit. This
bit is updated every time a frame is received.
[4:3] SBTH 00 Extended divider ratio for baud rate setting, as shown in Table 144.
[2:0] DIV 000 Binary divider (see Table 144).
DIV Result
000 Divide by 1
001
Divide by 2
010
Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Divide by 128
Table 143. UART Timer Fractional Divider SFR (SBAUDF, Address 0x9D)
Bit Mnemonic Default Description
7 UARTBAUDEN 0 UART baud rate enable. Set to enable UART timer to generate the baud rate.
When set, the SMOD bit (PCON, Address 0x87[7]), the TCLK bit (T2CON, Address 0xC8[4]), and the
RCLK bit (T2CON, Address 0xC8[5]) are ignored.
Cleared to let the baud rate be generated as per a standard 8052.
6 Not implemented Not implemented, write don’t care.
[5:0] SBAUDF 0 UART timer fractional divider.