Datasheet
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 134 of 156
Because Timer 2 has 16-bit autoreload capability, very low baud
rates are still possible. Timer 2 is selected as the baud rate generator
by setting RCLK and/or TCLK in the Timer/Counter 2 control
SFR (T2CON, Address 0xC8[5:4]). The baud rates for transmit
and receive can be simultaneously different. Setting RCLK and/or
TCLK puts Timer 2 into its baud rate generator mode, as shown in
Figure 108.
In this case, the baud rate is given by the following formula:
Mode 1 or Mode 3 Baud Rate =
( )
[ ]
( )
LRCAPHRCAP
f
CORE
2:26553616 −×
UART Timer Generated Baud Rates
The high integer dividers in a UART block mean that high speed
baud rates are not always possible. In addition, generating baud
rates requires the exclusive use of a timer, rendering it unusable
for other applications when the UART is required. To address
this problem, each ADE5166/ADE5169/ADE5566/ADE5569
has a dedicated baud rate timer (UART timer) specifically for
generating highly accurate baud rates. The UART timer can be
used instead of Timer 1 or Timer 2 for generating very accurate
high speed UART baud rates, including 115,200 bps. This timer
also allows a much wider range of baud rates to be obtained. In
fact, every desired bit rate from 12 bps to 393,216 bps can be
generated to within an error of ±0.8%. The UART timer also
frees up the other three timers, allowing them to be used for
different applications. A block diagram of the UART timer is
shown in Figure 107.
÷(1 + SBAUDF/64)
UART TIMER
Rx/Tx CLOCK
f
CORE
UARTBAUDEN
Rx CLOCK
Tx CLOCK
TIMER 1/TIMER 2
Rx CLOCK
FRACTIONAL
DIVIDER
0
0
1
1
TIMER 1/TIMER 2
Tx CLOCK
÷32
÷2
DIV + SBTH
07411-081
Figure 107. UART Timer, UART Baud Rate
Two SFRs, the enhanced serial baud rate control SFR (SBAUDT,
Address 0x9E) and UART timer fractional divider SFR (SBAUDF,
Address 0x9D), are used to control the UART timer. SBAUDT
is the baud rate control SFR; it sets up the integer divider (the DIV
bits, Bits[2:0]) and the extended divider (the SBTH bits, Bits[4:3])
for the UART timer.
The appropriate value to write to the DIV bits and the SBTH
bits can be calculated using the following formula, where f
CORE
is
defined in the POWCON SFR (see Table 26). Note that the DIV
value must be rounded down to the nearest integer.
( )
2log
16
log
×
=+
RateBaud
f
SBTHDIV
CORE
f
CORE
T2 PIN
(P1.4/T2/FP23)
T2EX PIN
(P1.3/T2EX/FP24)
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
RELOAD
EXEN2
CONTROL
TRANSITION
DETECTOR
EXF 2
TIMER 2
INTERRUPT
RCAP2L
RCAP2H
TIMER 2
OVERFLOW
2
16
16
RCLK
TCLK
Rx
CLOCK
Tx
CLOCK
0
0
1
1
10
SMOD
TIMER 1
OVERFLOW
C/T2 = 0
C/T2 = 1
NOTE: AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
07411-080
P1.4/T2/FP23
Figure 108. Timer 2, UART Baud Rates