Datasheet

ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 14 of 156
Table 9. SPI Slave Mode Timing Parameters (SPICPHA = 1)
Parameter Description Min Typ Max Unit
t
SS
SS
to SCLK edge 145 ns
t
SL
SCLK low pulse width 6 × t
CORE
1
ns
t
SH
SCLK high pulse width 6 × t
CORE
1
ns
t
DAV
Data output valid after SCLK edge 25 ns
t
DSU
Data input setup time before SCLK edge 0 ns
t
DHD
Data input hold time after SCLK edge 2 × t
CORE
1
+ 0.5 µs
t
DF
Data output fall time 19 ns
t
DR
Data output rise time 19 ns
t
SR
SCLK rise time 19 ns
t
SF
SCLK fall time 19 ns
t
SFS
SS
high after SCLK edge 0 ns
1
t
CORE
depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); t
CORE
= 2
CD
/4.096 MHz.
MSB
MOSI
BITS[6:1]
t
DHD
t
DSU
MSB IN
LSB IN
BITS[6:1]
LSB
t
DR
t
DF
t
DAV
MISO
t
SL
t
SH
t
SR
t
SF
t
SFS
t
SS
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS
07411-006
Figure 7. SPI Slave Mode Timing (SPICPHA = 1)