Datasheet

ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 140 of 156
SERIAL PERIPHERAL INTERFACE (SPI)
The ADE5166/ADE5169/ADE5566/ADE5569 integrate a complete
hardware serial peripheral interface on chip. The SPI is full duplex
so that eight bits of data are synchronously transmitted and simul-
taneously received. This SPI implementation is double buffered,
allowing users to read the last byte of received data while a new
byte is shifted in. The next byte to be transmitted can be loaded
while the current byte is shifted out.
The SPI port can be configured for master or slave operation.
The physical interface to the SPI is via the MISO (P0.5/MISO/ZX),
MOSI (P0.4/MOSI/SDATA), SCLK (P0.6/SCLK/T0), and
SS
(P0.7/
SS
/T1/RxD2) pins, while the firmware interface is via the
SFRs listed in
Table 150.
Note that the SPI pins are shared with the I
2
C pins. Therefore, the
user can enable only one interface at a time. The SCPS bit in the
configuration SFR (CFG, Address 0xAF[5]) selects which peri-
pheral is active.
SPI REGISTERS
Table 150. SPI SFR List
SFR Address Mnemonic R/W Length (Bits) Default Description
0x9A SPI2CTx W 8 0 SPI/I
2
C transmit buffer (see Table 151).
0x9B SPI2CRx R 8 0 SPI/I
2
C receive buffer (see Table 152).
0xE8 SPIMOD1 R/W 8 0x10 SPI Configuration SFR 1 (see Table 153).
0xE9 SPIMOD2 R/W 8 0 SPI Configuration SFR 2 (see Table 154).
0xEA SPISTAT R/W 8 0 SPI interrupt status (see Table 155).
Table 151. SPI/I
2
C Transmit Buffer SFR (SPI2CTx, Address 0x9A)
Bit Mnemonic Default Description
[7:0] SPI2CTx 0 SPI or I
2
C transmit buffer. When the SPI2CTx SFR is written, its content is transferred to the transmit
FIFO input. When a write is requested, the FIFO output is sent on the SPI or I
2
C bus.
Table 152. SPI/I
2
C Receive Buffer SFR (SPI2CRx, Address 0x9B)
Bit Mnemonic Default Description
[7:0] SPI2CRx 0 SPI or I
2
C receive buffer. When the SPI2CRx SFR is read, one byte from the receive FIFO output is
transferred to the SPI2CRx SFR. A new data byte from the SPI or I
2
C bus is written to the FIFO input.