Datasheet

Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 149 of 156
I/O PORTS
PARALLEL I/O
The ADE5166/ADE5169/ADE5566/ADE5569 use three input/
output ports to exchange data with external devices. In addition
to performing general-purpose I/O, some ports are capable of
driving an LCD or performing alternate functions for the periph-
erals available on chip. In general, when a peripheral is enabled, the
pins associated with it cannot be used as general-purpose I/Os. The
I/O port can be configured through the SFRs listed in Table 160.
Table 160. I/O Port SFRs
SFR Address Bit Addressable Description
P0 0x80 Yes Port 0
P1 0x90 Yes Port 1
P2 0xA0 Yes Port 2
EPCFG 0x9F No Extended port
configuration
PINMAP0 0xB2 No Port 0 weak
pull-up enable
PINMAP1 0xB3 No Port 1 weak
pull-up enable
PINMAP2 0xB4 No Port 2 weak
pull-up enable
The three bidirectional I/O ports have internal pull-ups that can
be enabled or disabled individually for each pin. The internal
pull-ups are enabled by default. Disabling an internal pull-up
causes a pin to become open drain. Weak internal pull-ups are
configured through the PINMAPx SFRs.
Figure 118 shows a typical bit latch and I/O buffer for an I/O pin.
The bit latch (one bit in the SFR of each port) is represented as a
Type D flip-flop, which clocks in a value from the internal bus
in response to a write-to-latch signal from the CPU. The Q out-
put of the flip-flop is placed on the internal bus in response to a
read latch signal from the CPU. The level of the port pin itself is
placed on the internal bus in response to a read pin signal from
the CPU. Some instructions that read a port activate the read
latch signal, and others activate the read pin signal. See the
Read-Modify-Write Instructions section for details.
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
Q
LATCH
DV
DD
Px.x
PIN
INTERNAL
PULL-UP
ALTERNATE
OUTPUT
FUNCTION
ALTERNATE
INPUT
FUNCTION
Q
CLOSED: PINMAPx.x = 0
OPEN: PINMAPx.x = 1
07411-090
Figure 118. Port 0 Bit Latch and I/O Buffer
Weak Internal Pull-Ups Enabled
A pin with weak internal pull-up enabled is used as an input by
writing a 1 to the pin. The pin is pulled high by the internal pull-
up, and the pin is read using the circuitry shown in Figure 118.
If the pin is driven low externally, it sources current because of
the internal pull-up.
A pin with internal pull-up enabled is used as an output by writing
a 1 or a 0 to the pin to control the level of the output. If a 0 is
written to the pin, it drives a logic low output voltage (V
OL
) and
is capable of sinking 1.6 mA.
Open Drain (Weak Internal Pull-Ups Disabled)
When the weak internal pull-up on a pin is disabled, the pin
becomes open drain. Use this open-drain pin as a high impedance
input by writing a 1 to the pin. The pin is read using the circuitry
shown in Figure 118. The open-drain option is preferable for
inputs because it draws less current than the internal pull-ups
that were enabled.
38 kHz Modulation
Each ADE5166/ADE5169/ADE5566/ADE5569 provides a 38 kHz
modulation signal. The 38 kHz modulation is accomplished by
internally XOR’ing the level written to the I/O pin with a 38 kHz
square wave. Then, when a 0 is written to the I/O pin, it is
modulated as shown in Figure 119.
38kHz MODULATION
SIGNAL
38kHz MODULATED
OUTPUT PIN
LEVEL WRITTEN
TO MOD38
07411-091
Figure 119. 38 kHz Modulation
Uses for this 38 kHz modulation include IR modulation of
a UART transmit signal or a low power signal to drive an LED.
The modulation can be enabled or disabled with the MOD38EN
bit in the configuration SFR (CFG, Address 0xAF[4]). The 38 kHz
modulation is available on eight pins, which are selected by the
MOD38 bits in the extended port configuration SFR (EPCFG,
Address 0x9F[7:0]).