Datasheet

Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 31 of 156
POWER SUPPLY ARCHITECTURE
The ADE5166/ADE5169/ADE5566/ADE5569 have two power
supply inputs, V
DD
and V
BAT
. They require only a single 3.3 V power
supply at V
DD
for full operation. A battery backup, or secondary
power supply, with a maximum of 3.7 V can be connected to the
V
BAT
input. Internally, the ADE5166/ADE5169/ADE5566/
ADE5569 connect V
DD
or V
BAT
to V
SWOUT
, which is used to derive
power for the ADE5166/ADE5169/ADE5566/ADE5569 circuitr y.
The V
SWOUT
output pin reflects the voltage at the internal power
supply (V
SWOUT
) and has a maximum output current of 6 mA. This
pin can also be used to power a limited number of peripheral com-
ponents. The 2.5 V analog supply (V
INTA
) and the 2.5 V supply for
the core logic (V
INTD
) are derived by on-chip linear regulators from
V
SWOUT
. Figure 32 shows the ADE5166/ADE5169/ADE5566/
ADE5569 power supply architecture.
POWER SUPPLY
MANAGEMENT
LDO
V
INTD
LDO
V
INTA
ADC
V
SW
ADC
SCRATCH PAD
LCD RTC
TEMPERATURE ADC
3.3V
MCU
ADE
SPI/I
2
C
UART
2.5V
V
DCIN
V
DD
V
BAT
V
SWOUT
BCTRL
07411-011
Figure 32. Power Supply Architecture
The ADE5166/ADE5169/ADE5566/ADE5569 provide automatic
battery switchover between V
DD
and V
BAT
based on the voltage
level detected at V
DD
or V
DCIN
. In addition, the BCTRL input can be
used to trigger a battery switchover. The conditions for switching
V
SWOUT
from V
DD
to V
BAT
and back to V
DD
are described in the
Battery Switchover section. V
DCIN
is an input pin that can be con-
nected to a dc signal of 0 V to 3.3 V. This input is intended for
power supply supervisory purposes and does not provide power
to the ADE5166/ADE5169/ADE5566/ADE5569 circuitry (see
the Battery Switchover section).
BATTERY SWITCHOVER
The ADE5166/ADE5169/ADE5566/ADE5569 monitor V
DD
,
V
BAT
, and V
DCIN
. Automatic battery switchover from V
DD
to V
BAT
can be configured based on the status of the V
DD
, V
DCIN
, or BCTRL
pin. Battery switchover is enabled by default. Setting Bit 1 in the
battery switchover configuration SFR (BATPR, Address 0xF5)
disables battery switchover so that V
DD
is always connected to
V
SWOUT
(see Table 19). The source of V
SWOUT
is indicated by Bit 6
in the peripheral configuration SFR (PERIPH, Address 0xF4),
which is described in Table 20. Bit 6 is set when V
SWOUT
is con-
nected to V
DD
and cleared when V
SWOUT
is connected to V
BAT
.
The battery switchover functionality provided by the ADE5166/
ADE5169/ADE5566/ADE5569 allows a seamless transition from
V
DD
to V
BAT
. An automatic battery switchover option ensures a
stable power supply to the ADE5166/ADE5169/ADE5566/
ADE5569, as long as the external battery voltage is above 2.75 V.
It allows continuous code execution even while the internal power
supply is switching from V
DD
to V
BAT
and back. Note that the energy
metering ADCs are not available when V
BAT
is used for V
SWOUT
.
Power supply management (PSM) interrupts can be enabled to
indicate when battery switchover occurs and when the V
DD
power
supply is restored (see the Power Supply Management (PSM)
Interrupt section).
Switching from V
DD
to V
BAT
The following three events switch the internal power supply
(V
SWOUT
) from V
DD
to V
BAT
:
• V
DCIN
< 1.2 V. When V
DCIN
falls below 1.2 V, V
SWOUT
switches
from V
DD
to V
BAT
. This event is enabled when the BATPRG
bits (Bits[1:0]) in the battery switchover configuration SFR
(BATPR, Address 0xF5) are set to 0b01.
• V
DD
< 2.75 V. When V
DD
falls below 2.75 V, V
SWOUT
switches
from V
DD
to V
BAT
. This event is enabled when the BATPRG
bits in the BATPR SFR are cleared.
• Falling edge on BCTRL. When the battery control pin,
BCTRL, goes low, V
SWOUT
switches from V
DD
to V
BAT
. This
external switchover signal can trigger a switchover to V
BAT
at any time. Setting the INT1PRG bits (Bits[3:1]) to 0bX01 in
the interrupt pins configuration SFR (INTPR, Address 0xFF)
enables the BCTRL pin (see
Table 17).
Switching from V
BAT
to V
DD
To switch V
SWOUT
from V
BAT
to V
DD
, all of the following events
must be true:
• V
DD
> 2.75 V. V
SWOUT
switches back to V
DD
after V
DD
remains
above 2.75 V.
• V
DCIN
> 1.2 V and V
DD
> 2.75 V. If the low V
DCIN
condition
is enabled, V
SWOUT
switches to V
DD
after V
DCIN
remains
above 1.2 V and V
DD
remains above 2.75 V.
• Rising edge on BCTRL. If the battery control pin is enabled,
V
SWOUT
switches back to V
DD
after BCTRL is high, and the
first or second bullet point is satisfied.
POWER SUPPLY MANAGEMENT (PSM) INTERRUPT
The power supply management (PSM) interrupt alerts the 8052
core of power supply events. The PSM interrupt is disabled by
default. Setting Bit 1 (EPSM) in the Interrupt Enable and Priority 2
SFR (IEIP2, Address 0xA9) enables the PSM interrupt (see
Table 83).
The power management interrupt enable SFR (IPSME,
Address 0xEC) controls the events that result in a PSM interrupt
(see Table 21).
Figure 33 illustrates how the PSM interrupt vector is shared among
the PSM interrupt sources. The PSM interrupt flags are latched
and must be cleared by writing to the power management interrupt
flag SFR (IPSMF, Address 0xF8), as described in Table 18.