Datasheet

ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 32 of 156
EPSR
FPSR
ESAG
FSAG
EVADC
FVADC
EBAT
FBAT
EBSO
FBSO
EVDCIN
FVDCIN
FPSM
EPSM
TRUE?
PENDING PSM
INTERRUPT
EPSR RESERVED ESAG RESERVED EVADC EBAT EBSO EVDCIN
FPSR FPSM FSAG RESERVED FVADC FBAT FBSO FVDCIN
PS2
PTI ES2 PSI EADE ETI EPSM ESI
IPSME ADDR. 0xEC
IPSMF ADDR. 0xF8
IEIP2 ADDR. 0xA9
NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN
07411-012
Figure 33. Power Supply Management Interrupt Sources
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE5166/ADE5169/ADE5566/ADE5569 can be configured
to generate a PSM interrupt when the source of V
SWOUT
changes
from V
DD
to V
BAT
, indicating battery switchover. Setting the EBSO
bit (Bit 1) in the power management interrupt enable SFR (IPSME,
Address 0xEC) enables this event to generate a PSM interrupt
(see Table 21).
The ADE5166/ADE5169/ADE5566/ADE5569 can also be con-
figured to generate an interrupt when the source of V
SWOUT
changes
from V
BAT
to V
DD
, indicating that the V
DD
power supply has been
restored. Setting the EPSR bit (Bit 7) in the power management
interrupt enable SFR (IPSME, Address 0xEC) enables this event to
generate a PSM interrupt.
The flags in the IPSMF SFR for these interrupts, FBSO (Bit 1)
and FPSR (Bit 7), are set regardless of whether the respective
enable bits are set. The battery switchover and power supply
restore event flags (FBSO and FPSR) are latched. These events
must be cleared by writing 0 to these bits. The VSWSOURCE bit
(Bit 6) in the peripheral configuration SFR (PERIPH, Address
0xF4) tracks the source of V
SWOUT
. The bit is set when V
SWOUT
is
connected to V
DD
and cleared when V
SWOUT
is connected to V
BAT
.
V
DCIN
ADC PSM Interrupt
The ADE5166/ADE5169/ADE5566/ADE5569 can be configured
to generate a PSM interrupt when V
DCIN
changes magnitude by
more than a configurable threshold. This threshold is set in the
temperature and supply delta SFR (DIFFPROG, Address 0xF3),
as described in Table 51. See the External Voltage Measurement
section for more information. Setting the EVADC bit (Bit 3) in
the power management interrupt enable SFR (IPSME, Address
0xEC) enables this event to generate a PSM interrupt.
The V
DCIN
voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to check
the change in V
DCIN
. Conversions can also be initiated by writing to
the start ADC measurement SFR (ADCGO, Address 0xD8), as
described in Table 52. The FVADC flag indicates when a V
DCIN
measurement is ready. See the External Voltage Measurement
section for details on how V
DCIN
is measured.
V
BAT
Monitor PSM Interrupt
The V
BAT
voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to check
the change in V
BAT
. The FBAT bit (Bit 2 in the IPSMF SFR) is
set when the battery level is lower than the threshold set in the
battery detection threshold SFR (BATVTH, Address 0xFA),
described in Table 53; or when a new measurement is ready in
the battery ADC value SFR (BATADC, Address 0xDF), described
in Table 55. See the Battery Measurement section for more infor-
mation. Setting the EBAT bit (Bit 2) in the power management
interrupt enable SFR (IPSME, Address 0xEC) enables this event
to generate a PSM interrupt.
V
DCIN
Monitor PSM Interrupt
The V
DCIN
voltage is monitored by a comparator. The FVDCIN
bit (Bit 0) in the power management interrupt flag SFR (IPSMF,
Address 0xF8) is set when the V
DCIN
input level is lower than 1.2 V.
Setting the EVDCIN bit (Bit 0) in the IPSME SFR enables this
event to generate a PSM interrupt. This event, which is associated
with the SAG monitoring, can be used to detect that a power
supply (V
DD
) is compromised and to trigger further actions prior to
initiating a switch from V
DD
to V
BAT
.